SAK-C167CS-4R40M CA+ Infineon Technologies, SAK-C167CS-4R40M CA+ Datasheet - Page 26

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SAK-C167CS-4R40M CA+

Manufacturer Part Number
SAK-C167CS-4R40M CA+
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAK-C167CS-4R40M CA+

Packages
PG-MQFP-144
Max Clock Frequency
40.0 MHz
Sram (incl. Cache)
11.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
24
Program Memory
32.0 KByte
The C167CS also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 4
time:
Table 4
Exception Condition
Reset Functions:
– Hardware Reset
– Software Reset
– W-dog Timer Overflow
Class A Hardware Traps:
– Non-Maskable Interrupt
– Stack Overflow
– Stack Underflow
Class B Hardware Traps:
– Undefined Opcode
– Protected Instruction
– Illegal Word Operand
– Illegal Instruction
– Illegal External Bus
Reserved
Software Traps
– TRAP Instruction
Data Sheet
Fault
Access
Access
Access
shows all of the possible exceptions or error conditions that can arise during run-
Hardware Trap Summary
Trap
Flag
NMI
STKOF
STKUF
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
Trap
Vector
RESET
RESET
RESET
NMITRAP
STOTRAP
STUTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
22
Vector
Location
00’0000
00’0000
00’0000
00’0008
00’0010
00’0018
00’0028
00’0028
00’0028
00’0028
00’0028
[2C
3C
Any
[00’0000
00’01FC
in steps
of 4
H
H
H
]
H
H
H
H
H
H
H
H
H
H
H
H
H
]
Trap
Number
00
00
00
02
04
06
0A
0A
0A
0A
0A
[0B
0F
Any
[00
7F
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
]
]
C167CS-4R
V2.2, 2001-08
C167CS-L
Trap
Priority
III
III
III
II
II
II
I
I
I
I
I
Current
CPU
Priority

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