SAK-C167CS-4R40M CA+ Infineon Technologies, SAK-C167CS-4R40M CA+ Datasheet - Page 62

• Manufacturer Part Number: SAK-C167CS-4R40M CA+
• Manufacturer: Infineon Technologies

Specifications of SAK-C167CS-4R40M CA+

• Packages: PG-MQFP-144
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 11.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 32.0 KByte

Direct Drive
When direct drive is configured (CLKCFG = 011
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of
f
f
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
For two consecutive TCLs the deviation caused by the duty cycle of
so the duration of 2TCL is always 1/
be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/
Data Sheet
CPU
OSC
.
TCL
(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
min
= 1/
f
OSC
f
CPU
× DC
directly follows the frequency of
min
(DC = duty cycle)
f
OSC
. The minimum value TCL
58
B
) the on-chip phase locked loop is
f
OSC
so the high and low time of
f
OSC
min
therefore has to
is compensated
C167CS-4R
f
V2.2, 2001-08
OSC
C167CS-L
.