AD9952 Analog Devices, AD9952 Datasheet
AD9952
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AD9952 Summary of contents
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... DDS Clock Timing & Control Logic SYNC 4 Control Registers M U System Clock X 4x-20x Clock Multipler IO Port One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 AD9952 DAC I-set 14 Aout DAC Aout System Clock 14 OSK PwrDwn Comparator Analog In + Clock Out ...
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... Control Function Register #1 (CFR1) Control Function Register #1 (CFR2) Other Register Descriptions REV. PrB 3/4/03 tuning word). The frequency tuning and control words are loaded into the AD9952 via a serial I/O port. The device includes an on- chip high speed comparator for applications requiring a square to form a digitally- wave output ...
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... Synchronization; Register Updates (I/O UPDATE) Functionality of the SyncClk and I/O UPDATE Figure D- I/O Synchronization Block Diagram Figure E - I/O Synchronization Timing Diagram Synchronizing Multiple AD9952s Using a Single Crystal To Drive Multiple AD9952 Clock InputsError! Bookmark not defined. Serial Port Operation Instruction Byte Serial Interface Port Pin Description MSB/LSB Transqfers ...
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... PRELIMINARY TECHNICAL DATA AD9952 PRELIMINARY ELECTRICAL SPECIFICATIONS =+1.8 V ±5%, R (Unless otherwise noted Multiplier enabled at 20×) Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Disabled REFCLK Multiplier Enabled at 4X REFCLK Multiplier Enabled at 20X Input Capacitance Input Impedance Duty Cycle Duty Cycle with REFCLK Multiplier Enabled ...
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... 1.25 I 0.6 I 2 1.35 I 0.4 Analog Devices, Inc. AD9952 dBc Units dBc dBc pF kΩ µ MHz ps RMS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... DAC_BP, and that the recommended PLL loop filter values are used. 5 SYSCLK refers to the actual clock frequency used on-chip by the AD9952. If the Reference Clock Multiplier is used to multiply the external reference frequency, then the SYSCLK frequency is the external frequency multiplied by the Reference Clock Multiplier multiplication factor ...
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... Figure 1 AD9952 Pinmap Page RESET PwrDwnCtl 34 DVDD 33 DGND AGND 32 COMP_INB 31 30 COMP_IN AVDD 29 ...
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... A resistor (3.85KΩ nominal) connected from AGND to DAC_Rset establishes the reference current for the DAC. O Comparator Output I Comparator input I Comparator complementary input I Input pin used as an external power down control. See the External Power Down Control section of this document for details. Page 8 AD9952 Analog Devices, Inc. ...
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... SYNC_CLK REV. PrA 3/4/03 I Active high hardware reset pin. Assertion of the RESET pin forces the AD9952 to the initial state, as described in the IO Port Register map. I Asynchronous active high reset of the serial port controller. When high, the current IO operation is immediately terminated enabling a new IO operation ...
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... The AD9952 frequency tuning word(s) are unsigned numbers, where 80000000(hex) represents the highest output frequency possible, commonly referred to as the Nyquist frequency. Values ranging from than 80000001(hex) to FFFFFFFF (hex) will be expressed as aliased frequencies less than Nyquist. An example using a 3-bit phase accumulator will illustrate this principle. For a tuning word of 001, the phase accumulator output (PAO) increments from all zeros to all ones and repeats when the accumulator overflows after clock cycle number 8 ...
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... The AD9952 supports various clock methodologies. Support for differential or single-ended input clocks, enabling of an on-chip oscillator and/or phase-locked loop (PLL) multiplier are all controlled via user programmable bits. The AD9952 may be configured in one of six operating modes to generate the system clock. The modes are configured using the ClkModeSelect pin, CFR2< ...
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... The PLL is bypassed by programming a value outside the range of 4-20 (decimal). When bypassed, the PLL is shut down to conserve power. DAC Output The AD9952 incorporates an integrated 14-bit current output DAC. Two complementary outputs provide a combined full-scale output current (I common-mode noise that might be present at the DAC output, offering the advantage of an increased signal-to-noise ratio ...
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... Motorola 6905/11 SPI and Intel 8051 SSR protocols. The interface allows read/write access to all registers that configure the AD9952. MSB first or LSB first transfer formats are supported. In addition, the AD9952’s serial interface port can be configured as a single pin I/O (SDIO), which allows a two-wire interface or two unidirectional pins for in/out (SDIO/SDO), which enables a three wire interface ...
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... PRELIMINARY TECHNICAL DATA AD9952 Register Map Register Bit (MSB) Name Range Bit 7 (Serial (Internal address) address) <7:0> Digital (00h) Power Down Control Function <15:8> Register #1 Open (01h) (CFR1) <23:16> Automatic (00h) Sync (02h) Enable <31:24> (03h) Control Function <7:0> Register #2 (04h) (CFR2) <15:8> (01h) (05h) <23:16> (06h) Amplitude < ...
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... PRELIMINARY TECHNICAL DATA Control Register Bit Descriptions Control Function Register #1 (CFR1) The CFR1 is used to control the various functions, features, and modes of the AD9952. The functionality of each bit is detailed below. CFR1<26>: Amplitude ramp rate load control bit. When CFR1<26> (default), the amplitude ramp rate timer is loaded only upon timeout (timer ==1) and is NOT loaded due to an I/O UPDATE input signal. When CFR1< ...
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... PRELIMINARY TECHNICAL DATA CFR1<22>: Software Manual Synchronization Mode. When CFR1<22> (default), the manual synchronization of multiple AD9952s feature is inactive. When CFR1<22> the software controlled manual synchronization feature is executed. The SYNC_CLK rising edge is advanced by one SYSCLK cycle and this bit is cleared. To advance the rising edge multiple times, this bit needs to be set for each advance ...
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... CFR1<9>: SDIO Input Only. When CFR1<9> (default), the SDIO pin has bi-directional operation (2-wire serial programming mode). When CFR1<9> the serial data I/O pin (SDIO) is configured as an input only pin (3-wire serial programming mode). REV. PrA 3/4/03 Page 17 AD9952 Analog Devices, Inc. ...
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... PLL, oscillator, and clock input circuitry is NOT powered down. When CFR1<3> the external power down mode selected is the “full power down” mode. In this mode, when the PwrDwnCtl input pin is high, all functions are REV. PrA 3/4/03 Page 18 AD9952 Analog Devices, Inc. ...
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... When CFR2<11> (default) the High Speed Sync enhancement is off. When CFR2<11> the High Speed Sync enhancement is on. See the Synchronizing Multiple AD9952s section of this document for details. CFR2<10>: Hardware Manual Sync Enable bit. When CFR2<10> (default) the Hardware Manual Sync function is off. ...
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... The ARR register stores the 8-bit Amplitude Ramp Rate used in the Auto OSK mode, that is CFR1<25>=1, CFR<24>=1. This register programs the rate the amplitude scale factor counter increments or decrements. In the OSK is set to manual mode, CFR1<25>=1 CFR<24>= OSK enable is cleared CFR1<25>=0, this register has no affect on device operation. REV. PrA 3/4/03 Page 20 AD9952 Analog Devices, Inc. ...
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... Continuous and “Clear and Release” Phase Accumulator Clear Functions The AD9952 allows for a programmable continuous zeroing of the phase accumulator as well as a “clear and release”, or automatic zeroing function. Each feature is individually controlled via bits the CFR1. CFR1<13> is the Automatic Clear Phase Accumulator bit. CFR1<10> continuously clears the Phase Accumulator ...
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... However, both the speed of the I/O Port and the frequency of sysclk limit the rate at which phase modulation can be performed. Phase/Amplitude Dithering The AD9952 DDS core includes optional phase and/or amplitude dithering controlled via the CFR1<20:16> bits. Phase dithering is the randomization of the state of the least significant bits of each phase word. ...
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... PRELIMINARY TECHNICAL DATA Shaped On-Off Keying General Description: The Shaped On-Off keying function of the AD9952 allows the user to control the ramp-up and ramp-down time of an “on-off” emission from the DAC. This function is used in “burst transmissions” of digital data to reduce the adverse spectral impact of short, abrupt bursts of data ...
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... Method one is by changing the OSK input pin. When the OSK input pin changes state the ASFR value is loaded into the ramp rate timer, which then proceeds to count down as normal. REV. PrA 3/4/03 Increment/decrement size Page 24 AD9952 Analog Devices, Inc. ...
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... AD9952’s internal DDS clock. This is accomplished by forcing any external hardware to obtain its timing from SyncClk. External hardware that is timed using the SyncClk signal can then be used to provide the I/O UPDATE signal to the AD9952. The I/O UPDATE signal coupled with SyncClk is used to transfer internal buffer register contents into the Control Registers of the device ...
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... Edge Detection Logic SYNCCLK Gating I/O Buffer Latches Figure D- I/O Synchronization Block Diagram A B Data(2) Data(2) The device registers an I/O Update at point A. The data is tranferred from the asynchronously loaded I/O buffers at point B. Page I/O UPDATE SCLK SDI CS Data(3) Analog Devices, Inc. AD9952 Data(3) ...
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... The AD9952 crystal oscillator output signal is available on the CrystalOut pin, enabling one crystal to drive multiple AD9952s. In order to drive multiple AD9952s with one crystal, the CrystalOut pin of the AD9952 using the external crystal should be connected to the REFCLK input of the other AD9952. The CrystalOut pin is static until the CFR2<1> bit is set, enabling the output. The drive strength of the CrystalOut pin is typically very low, so this signal should be buffered prior to using it to drive any loads ...
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... At the completion of any communication cycle, the AD9952 serial port controller expects the next 8 rising SCLK edges to be the instruction byte of the next communication cycle.All data input to the AD9952 is registered on the rising edge of SCLK. All data is driven out of the AD9952 on the falling edge of SCLK. Figures are useful in understanding the general operation of the AD9952 Serial Port ...
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... R/-Wb—Bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. Logic high indicates read operation. Logic zero indicates a write operation. REV. PrA 3/4/ Table 6 Instruction Byte Page 29 AD9952 D1 LSB A1 A0 Analog Devices, Inc. ...
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... IO operation is complete. All data written to (read from) the AD9952 must be (will be) in MSB first order. If the LSB mode is active, the serial port controller will generate the least significant byte address first followed by the next greater significant byte addresses until the IO operation is complete ...
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... Since the Amplitude Scale Factor register is two bytes wide, this ends the communication cycle. Notes on Serial Port Operation 1) The AD9952 serial port configuration bits reside in bits 8 and 9 of CFR1 (address 00h). The configuration changes immediately upon writing to this register. For multi-byte transfers, writing to this register may occur during the middle of a communication cycle ...
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... CFR1<3> bit. When the PwrDwnCtl input pin is low, the external power down control is inactive. When the CFR1<3> bit is zero, and the PwrDwnCtl input pin is high, the AD9952 is put into a “fast recovery power down” mode. In this mode, the digital logic and the DAC digital logic are powered down ...
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... PRELIMINARY TECHNICAL DATA AD9952 Application Suggestions REFCLK Figure F Synthesized L.O For Upconversion/DownConversion Ref Signal Filter Figure G Digitally Programmable “Divide-by-N” Function in PLL Figure H Frequency Agile Clock Generator REV. PrA 3/4/03 RF/IF Input AD9952 LPF Phase Loop Comparator Filter AD9952 Tuning Word Tuning Word Iout ...
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... PRELIMINARY TECHNICAL DATA Frequency Saw Crystal Frequency Figure I Two AD9952s Synchronized to Provide I & Q Carriers with Independent Phase Offsets for Nulling REV. PrA 3/4/03 Phase Tuning Offset Word Word 1 REFCLK AD9952 DDS Iout LPF REFCLK Crystal Out Sync Out Sync In AD9952 DDS Iout ...