ADP3188 Analog Devices, ADP3188 Datasheet
ADP3188
Available stocks
Related parts for ADP3188
ADP3188 Summary of contents
Page 1
... Next-generation Intel processors VRM modules GENERAL DESCRIPTION The ADP3188 is a highly efficient multiphase synchronous buck switching regulator controller optimized for converting main supply into the core supply voltage required by high per- formance Intel® processors. It uses an internal 6-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0 ...
Page 2
... Ramp Resistor Selection............................................................ 20 COMP Pin Ramp ....................................................................... 20 Current Limit Setpoint .............................................................. 20 Feedback Loop Compensation Design.................................... 20 C Selection and Input Current di/dt Reduction.................. 22 IN Tuning the ADP3188 ................................................................. 22 DC Loadline Setting .............................................................. 22 AC Loadline Setting............................................................... 23 Initial Transient Setting ......................................................... 23 Layout and Component Placement ......................................... 24 General Recommendations .................................................. 24 Power Circuitry Recommendations .................................... 24 Signal Circuitry Recommendations ...
Page 3
... CSSUM – CSREF, A Figure 3 I BIAS(CSSUM) GBW (CSA CSCOMP CSSUM and CSREF ∆V Figure CSCOMP V SW(X)CM R SW( SW(X) I SW( SW(X) ∆I SW( SW(X) Rev Page ADP3188 Min Typ Max Unit 0.7 3.1 V −9.5 +9.5 mV 0.05 % µA 14 15.5 17 µA 100 140 µA 500 20 MHz 25 V/µs 0.4 V ...
Page 4
... ADP3188 Parameter CURRENT LIMIT COMPARATOR Output Voltage Normal Mode Shutdown Mode Output Current, Normal Mode 2 Maximum Output Current Current Limit Threshold Voltage Current Limite Setting Ratio DELAY Normal Mode Voltage DELAY Overcurrent Threshold Latch-Off Delay Time SOFT START Output Current, Soft-Start Mode ...
Page 5
... CSSUM 17 1kΩ CSREF 16 1.0V CSCOMP – 1V GND Figure 3. Current Sense Amplifier V OS ADP3188 VCC 12V 10kΩ COMP 9 CSCOMP 200kΩ 18 100nF 200kΩ CSSUM 17 ∆V CSREF 16 1.0V GND 19 ∆ – FB ∆V = 80mV ∆V = 0mV FB Figure 4. Positioning Voltage ADP3188 ...
Page 6
... ADP3188 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC FBRTN VID0 – VID5, EN, DELAY, ILIMIT, CSCOMP, RT, PWM1 – PWM4, COMP SW1 – SW4 All Other Inputs and Outputs Storage Temperature Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (θ Lead Temperature Soldering (10 sec) ...
Page 7
... When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8375 V to 1.6 V (see Table 4). Leaving all of the VID pins open results in the ADP3188 going into No CPU mode, shutting off its PWM outputs and pulling the PWRGD output low. ...
Page 8
... ADP3188 TYPICAL PERFORMANCE CHARACTERISTICS 100 150 R VALUE (kΩ) T Figure 6. Master Clock Frequency vs. R 200 250 300 T Rev Page 5 25°C A 4-PHASE OPERATION 5.2 5.1 5.0 4.9 4.8 4.7 4.6 0 0.5 1 1.5 2 2.5 3 OSCILLATOR FREQUENCY (MHz) Figure 7. Supply Current vs. Oscillator Frequency 3.5 4 ...
Page 9
... Also, more than one output can the same time for overlapping phases. MASTER CLOCK FREQUENCY The clock frequency of the ADP3188 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 6. To determine the frequency per phase, the clock is divided by the number of phases in use ...
Page 10
... CURRENT CONTROL MODE AND THERMAL BALANCE The ADP3188 has individual inputs for each phase, which are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system, which has been optimized for initial current balance accuracy and dynamic thermal balancing during operation ...
Page 11
... PWRGD threshold, a soft- start cycle is initiated. The latch-off function can be reset by either removing and reapplying VCC to the ADP3188 pulling the EN pin low for a short time. To disable the short-circuit latch-off function, the external resistor to ground should be left open, and a high value (> ...
Page 12
... ADP3188 Table 4. VID Codes for the ADP3188 VID4 VID3 VID2 VID1 VID0 ...
Page 13
... UVLO threshold, and the EN pin must be higher than its logic threshold. If UVLO is less than the threshold or the EN pin is a logic low, the ADP3188 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and holds the ILIMIT pin at ground. ...
Page 14
... ADP3188 *FOR A DESCRIPTION OF OPTIONAL R RESISTORS, SEE THE THEORY OF OPERATION SECTION. SW CPU FROM Figure 10. Typical VR 10.1 Application Circuit Rev Page ...
Page 15
... Switching frequency per phase (f SW SETTING THE CLOCK FREQUENCY The ADP3188 uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (R frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and of the input and output capacitors ...
Page 16
... ADP3188 The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 320 nH inductor is a good starting point and gives a calculated ripple current The inductor should not saturate at the peak current of 35.5 A and should be able to handle the sum of the power dissipation caused by the average current the winding and core loss ...
Page 17
... Choosing CS1 CS2 . The value of R can be found using B B − VID ONL − 281 Ω µA ADP3188 , and R using × − × − − (8) (9) (10) = CS1 yields (11) ...
Page 18
... ADP3188 C SELECTION OUT The required output decoupling for the regulator is typically recommended by Intel for various processors and platforms. One can also use some simple design guidelines to determine what is required. These guidelines are based on having both bulk and ceramic capacitors in the system. ...
Page 19
... The maximum output current (I ) determines the R O requirement for the low-side (synchronous) MOSFETs. With the ADP3188, currents are balanced between phases, thus the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (n ). With conduction losses SF being dominant, the following expression shows the total power ...
Page 20
... this example, the overall ramp signal is 0.49 V. CURRENT LIMIT SETPOINT To select the current limit setpoint, first find the resistor value for R . The current limit threshold for the ADP3188 is set with LIM source (V ) across R with a gain of 10.4 mV/µA (A LIM LIM ...
Page 21
... where, for the ADP3188 the PCB resistance from the bulk capacitors to the ceramics and where R DS MOSFET on resistance per phase. In this example, A equals 0. approximately 0.5 mΩ (assuming a 4-layer, 1 ounce motherboard), and L is 350 pH for the eight Al-Poly X capacitors ...
Page 22
... OUTPUT CURRENT (A) Figure 14. Efficiency of the Circuit of Figure 10 vs. Output Current ( R CS1 NEW TUNING THE ADP3188 1. Build a circuit based on the compensation values computed from the design spreadsheet. 2. Hook up the dc load to circuit, turn it on, and verify its operation. Also check for jitter at no-load and full-load. ...
Page 23
... You need more capacitance or you have to make the inductor values smaller. (If you change inductors, you need to start the design again using the spreadsheet and this tuning procedure.) (38) for the CS and ACDRP Rev Page ADP3188 is the final desired value. DROOP V DROOP V TRAN1 V TRAN2 Figure 16. Transient Setting Waveform ) ...
Page 24
... If critical signal lines (including the output voltage sense lines of the ADP3188) must cross through power circuitry best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier ...
Page 25
... BSC 1.20 MAX 0.30 0.20 0.19 SEATING 0.09 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 18. 28-Lead This Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters Package Description Thin Shrink SOIC 13” Reel Rev Page 6.40 BSC 8 ° 0.75 0 ° 0.60 0.45 Package Option Quantity per Reel RU-28 2500 ADP3188 ...
Page 26
... ADP3188 NOTES Rev Page ...
Page 27
... NOTES Rev Page ADP3188 ...
Page 28
... ADP3188 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04835–0–4/04(0) Rev Page ...