74HCT2G125DP,125 NXP Semiconductors, 74HCT2G125DP,125 Datasheet - Page 6

• Manufacturer Part Number: 74HCT2G125DP,125
• Description: IC BUFF DVR TRI-ST DL 8TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT2G125DP,125

• Package / Case: 8-TSSOP
• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Current - Output High, Low: 6mA, 6mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: HCT
• Number Of Channels Per Chip: 2
• Polarity: Non-Inverting
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 6 mA
• Input Bias Current (max): 20 uA
• Low Level Output Current: 6 mA
• Minimum Operating Temperature: - 40 C
• Output Type: 3-State
• Propagation Delay Time: 15 ns (Typ) @ 4.5 V
• Number Of Lines (input / Output): 2 / 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4285-2; 74HCT2G125DP-G; 935270086125

NXP Semiconductors
Table 8.
Voltages are referenced to GND (ground = 0 V); C
[1]
[2]
[3]
74HC_HCT2G125_4
Product data sheet
Symbol Parameter
t
t
t
C
74HCT2G125
t
t
t
t
C
en
dis
t
pd
en
dis
t
PD
PD
All typical values are measured at T
t
t
t
t
C
P
f
f
C
V
N = number of inputs switching;
pd
en
dis
t
i
o
(C
D
CC
PD
= input frequency in MHz;
L
is the same as t
= output frequency in MHz;
is the same as t
is the same as t
= output load capacitance in pF;
is the same as t
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
enable time
disable time nOE to nY; see
transition
time
power
dissipation
capacitance
propagation
delay
enable time
disable time nOE to nY; see
transition
time
power
dissipation
capacitance
PD
V
Dynamic characteristics
CC
2
V
CC
f
o
2
) = sum of outputs.
THL
PLH
PZL
f
PLZ
i
and t
Conditions
nOE to nY; see
see
per buffer; V
nA to nY; see
nOE to nY; see
V
V
see
per buffer;
V
and t
N + (C
and t
and t
CC
CC
I
V
V
V
V
V
V
V
V
V
output enabled
output disabled
V
V
output enabled
output disabled
= GND to V
TLH
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
Figure 6
Figure
PZH
= 4.5 V
= 4.5 V
PHL
PHZ
.
= 2.0 V
= 4.5 V
= 6.0 V
= 2.0 V
= 4.5 V
= 6.0 V
= 2.0 V
= 4.5 V
= 6.0 V
= 4.5 V
= 5.0 V; C
L
.
.
.
V
6; V
CC
amb
I
= GND to V
2
…continued
Figure 6
CC
= 25 C.
CC
Figure 7
Figure 7
Figure
Figure
f
L
o
) where:
= 4.5 V
= 15 pF
1.5 V
7;
7;
CC
L
= 50 pF unless otherwise specified; for test circuit see
Rev. 04 — 4 July 2008
D
in W).
[2]
[2]
[2]
[3]
[2]
[2]
[2]
[2]
[3]
74HC2G125; 74HCT2G125
T
Min
amb
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= 40 C to +85 C T
Typ
40
11
24
12
10
18
11
15
12
15
15
11
8
6
5
1
6
1
[1]
Max
115
125
23
20
25
21
75
15
13
31
35
31
15
-
-
-
-
-
Dual buffer/line driver; 3-state
amb
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= 40 C to +125 C Unit
© NXP B.V. 2008. All rights reserved.
Figure
Max
135
150
27
23
30
26
90
18
15
38
42
38
18
-
-
-
-
-
8.
6 of 14
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
ns
ns
ns
ns
ns
pF
pF