74HC1G126GW,125 NXP Semiconductors, 74HC1G126GW,125 Datasheet - Page 6

IC BUS BUFF DVR TRI-ST 5TSSOP

74HC1G126GW,125

Manufacturer Part Number
74HC1G126GW,125
Description
IC BUS BUFF DVR TRI-ST 5TSSOP
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheet

Specifications of 74HC1G126GW,125

Package / Case
SC-70-5, SC-88A, SOT-323-5, SOT-353, 5-TSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
1
Current - Output High, Low
7.8mA, 7.8mA
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
HC
Number Of Channels Per Chip
1
Polarity
Non-Inverting
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 7.8 mA
Low Level Output Current
7.8 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
24 ns (Typ) @ 2 V or 10 ns (Typ) @ 4.5 V or 9 ns (Typ) @ 6 V
Number Of Lines (input / Output)
1 / 1
Logical Function
Buffer/Line Driver
Number Of Elements
1
Number Of Channels
1
Number Of Inputs
1
Number Of Outputs
1
Operating Supply Voltage (typ)
5V
Package Type
TSSOP
Operating Supply Voltage (max)
6V
Operating Supply Voltage (min)
2V
Quiescent Current
20uA
Technology
CMOS
Pin Count
5
Mounting
Surface Mount
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74HC1G126GW-G
74HC1G126GW-G
935245710125
NXP Semiconductors
12. Waveforms
Table 9.
74HC_HCT1G126_4
Product data sheet
Type
74HC1G126
74HCT1G126
Fig 5. The input (A) to output (Y) propagation delays
Fig 6. The 3-state enable and disable times
Measurement points are given in
Measurement points are given in
Measurement points
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
OE input
output
output
Input
V
0.5
1.3 V
M
V
Y output
A input
CC
Table
Table
GND
GND
V
CC
V
I
9.
9.
GND
V
I
V
Rev. 04 — 20 July 2007
M
enabled
t
output
PLZ
t
PHZ
V
M
V
V
M
74HC1G126; 74HCT1G126
V
GND to V
GND to 3.0 V
t
OL
PHL
V OH
I
+ 0.3 V
0.3 V
disabled
output
CC
t
PZL
t
PZH
mna121
t
PLH
V
M
V
M
Bus buffer/line driver; 3-state
output
enabled
mna129
Output
V
0.5
1.3 V
M
V
CC
© NXP B.V. 2007. All rights reserved.
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