CD2401 Intel, CD2401 Datasheet - Page 110

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CD2401

Manufacturer Part Number
CD2401
Description
Multi-protocol Communications Controller
Manufacturer
Intel
Datasheet
CD2401 — Multi-Protocol Communications Controller
8.2.9.2
8.2.9.3
8.2.9.4
110
Register Name: SCHR2
Register Description: Special Character 2
Default Value: x’00
Access: Byte Read/Write
Register Name: SCHR3
Register Description: Special Character 3
Default Value: x’00
Access: Byte Read/Write
Register Name: SCHR4
Register Description: Special Character 4
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 7
Bit 7
Note: SCHR3 and 4 are not stripped from the datastream if FCT mode is enabled.
Special Character Register 2 (SCHR2)
SCHR1 and 2 are used in conjunction with the SCDE bit (COR3[4]) to detect specific incoming
characters. When both the SCDE and TxIBE (COR2[6]) bits are set, they define the in-band flow
control characters XON and XOFF. The values are user-defined, regardless how used.
SCHR1 = XON
SCHR2 = XOFF
In addition to the SCDE and TxIBE bits, if the FCT bit (COR3[5]) is set when flow control
characters are received, they are stripped from the datastream.
Special Character Register 3 (SCHR3)
Special Character Register 4 (SCHR4)
SCHR3 and 4 are used in conjunction with the ESCDE bit (COR3[7]) to detect characters in the
receive datastream and generate receive special character interrupts.
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
User-Defined Special Character
User-Defined Special Character
User-Defined Special Character
Bit 4
Bit 4
Bit 4
XOFF Character
Bit 3
Bit 3
Bit 3
Bit 2
Bit 2
Bit 2
Motorola Hex Address: x’1E
Motorola Hex Address: x’1C
Motorola Hex Address: x’1D
Bit 1
Bit 1
Bit 1
Intel Hex Address: x’1D
Intel Hex Address: x’1E
Intel Hex Address: x’1F
Datasheet
Bit 0
Bit 0
Bit 0

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