CD2401 Intel, CD2401 Datasheet - Page 92

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
8.0
8.1
8.1.1
8.1.2
92
Register Name: GFRCR
Register Description: Global Firmware Revision Code
Default Value: x’0D
Access: Byte Read/Write
Register Name: CAR
Register Description: Channel Access
Default Value: x’03
Access: Byte Read/Write
Bit 7
Bit 7
Detailed Register Descriptions
Global Registers
Global Firmware Revision Code Register (GFRCR)
This register serves two functions in providing the host with information about the CD2401. When
the CD2401 is initialized by a hardware RESET* signal or by a software ‘Reset All’ command
issued through any CCR, the CD2401 zeros this register at the start of the initialization. At the
conclusion of the initialization, the CD2401 writes the firmware revision code to the GFRCR. All
valid CD2401 revision codes are non-zero, the revision code is incremented by one with each new
release (for example, GFRCR for Revision M = 0D hex).
Host software must confirm that the GFRCR contents are non-zero before proceeding to configure
the CD2401 for normal operation.
Channel Access Register (CAR)
This register contains the channel number used for the channel-oriented host read/write operations
when the host is not in an interrupt service routine. The CD2401 supplies the interrupting channel
number during all interrupt service operations. The CAR contents are not used during interrupt
service. Note that this indicates that an interrupt service routine is restricted to accessing only the
register set of the interrupting Channel and Global registers.
Bits 7:2
Bits 1:0
Bit 6
Bit 6
Reserved – must be written as ‘0’; read back as a ‘don’t care’.
Channel number
Bit 5
Bit 5
Reserved
Firmware Revision Code
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Motorola Hex Address: x’EE
Motorola Hex Address: x’81
Bit 1
Bit 1
C1
Intel Hex Address: x’EC
Intel Hex Address: x’82
Datasheet
Bit 0
Bit 0
C0