CD2401 Intel, CD2401 Datasheet - Page 89

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

7.1
7.2
Datasheet
Global Initialization
The following code segment is an example of global initialization. The host waits for a hardware
reset, determined by a non-zero value in the GFRCR. A ‘Reset All’ command is sent to the
CD2401 by the CCR. The CD2401 internal processor will put a non-zero value into the GFRCR
when initialization is complete.
It is a good practice to manually clear the GFRCR before issuing the ‘Reset All’ command, as it
takes a finite amount of time for the internal processor to detect the presence of the command and
clear the register. If the host is sufficiently fast, it might read the GFRCR before the command
execution commences and incorrectly assume the command is complete. Note, unlike all other
CCR commands, the clearing the CCR is not an indication of ‘Reset All’ command completion;
clearing the CCR is a normal process of the internal register reset operation during ‘Reset All’
command execution, and occurs long before the reset operation is complete. When the GFRCR is
loaded with the firmware revision number, the command is complete.
The PILRs should be loaded with the value that will appear on the seven address lines (A[6:0])
during interrupt acknowledge cycles. The TPR loads the dividing counter that provides input to
each of the other timers in the CD2401. The DMA Mode and Bus Error Count registers are used in
DMA modes only. After the global portion is done, the Per-Channel registers need to be initialized.
Transfers and interrupts should be enabled after all other initialization is complete.
// Global Initialization
// per-channel initialization
Async Interrupt Setup Example
This section contains a code example for an asynchronous channel running at 19,200 bps, with
8 bits/character, 1 Stop bit, and no parity. The sample code enables in-band flow control and
implied XON mode. This code assumes that the proper channel is set by the CAR.
while( !inportb( GFRCR ) )
outportb( GFRCR, 0x00 );
outportb( CCR, RESET_ALL );
while( !inportb( GFRCR ) )
outportb( PILR1, 0x02 );
outportb( PILR2, 0x04 );
outportb( PILR3, 0x06 );
outportb( TPR, 0x40 );
outportb( BERCNT, 0 );
outportb( DMR, 0 );
for( i=0; i<4; i++ ) {
}
outportb( LIVR, 0x40 );
outportb( RCOR, 0 );
outportb( IER, TX_DATA|RX_DATA ); // enable interrupts
outportb( CAR, i );
init_chan( cor, bpr );
outportb( CMR, MODE );
outportb( CCR, INIT_CH | EN_RX | EN_TX );
while( inportb(CCR) )
; // wait
; // wait
Multi-Protocol Communications Controller — CD2401
// Receive clock option
// wait for hardware reset
// manually clear GFRCR
// Reset command
// wait for reset command
; // wait
// Priority Interrupt
// Level registers
// Set timer prescale
// Bus error count
// DMA mode — 16-bit
// set channel number
// initialize channel
// set protocol/DMA or Intr
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