CD2401 Intel, CD2401 Datasheet - Page 133

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

8.5.2.5
8.5.2.6
Datasheet
Register Name: RFOC
Register Description: Receive FIFO Output Count
Default Value: x’00
Access: Byte Read only
Register Name: RDR
Register Description: Receive Data
Default Value: x’00
Access: Byte Read only
Bit 7
Bit 7
D7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bits 2:0
Receive FIFO Output Count (RFOC)
Bits 7:5
Bits 4:0
Receive Data Register (RDR)
Bit 6
Bit 6
D6
0
is available in the A/BRCBAR. In response to a bus error status, the host has two
possible options
1.Retry from the next position in the buffer.
2.Terminate this buffer by setting REOIR[7] and move onto the next.
End of Frame
Reception of a data frame is complete (Sync DMA mode only).
End of Buffer
The end of a receive buffer is reached. Used only for DMA supported transmission.
The end of one of the host-supplied receive buffers is reached.
Reserved – always returns ‘0’ when read.
Buffer A/Buffer B
Status occurs during buffer A or buffer B data transfer.
0 = Buffer A
1 = Buffer B
Reserved – always returns ‘0’ when read
Reserved – always returns ‘0’ when read.
Receive Data Count [4:0]
If the receive channel is interrupt driven, a non-zero value in this bit field is the num-
ber of data characters available for transfer within the current receive interrupt.
Bit 5
Bit 5
D5
0
RxCt4
Bit 4
Bit 4
D4
Multi-Protocol Communications Controller — CD2401
RxCt3
Bit 3
Bit 3
D3
RxCt2
Bit 2
Bit 2
D2
Motorola Hex Address: x’30
Motorola Hex Address: x’F8
RxCt1
Bit 1
Bit 1
D1
Intel Hex Address: x’F8
Intel Hex Address: x’33
RxCt0
Bit 0
Bit 0
D0
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