PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 127

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
9.37 Microprocessor Interface
PROPRIETARY AND CONFIDENTIAL
The Microprocessor Interface Block provides normal and test mode registers, the
interrupt logic, and the logic required to connect to the Microprocessor Interface.
The normal mode registers are required for normal operation, and test mode
registers are used to enhance the testability of the TEMAP-84.
The Register Memory Map in Table 9 shows where the normal mode registers
are accessed. The resulting register organization splits into sections: Master
configuration registers, T1/E1 registers, DS3 M13 multiplexing registers,
SONET/SDH mapping registers and SBI registers.
On power up reset the TEMAP-84 defaults to 1.544 kbit/s tributaries multiplexed
into the three M13 multiplexers using the DS3 M23 multiplex format. For proper
operation some register configuration is necessary. System side access defaults
to the SBI bus without any tributaries enabled which will leave the SBI Drop bus
tristated. By default interrupts will not be enabled, automatic alarm generation is
disabled, a dual rail DS3 LIU interface is expected and an external transmit
reference clock is required.
Table 9
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
Address
- Register Memory Map
Revision
Reference Clock Select
Recovered Clock#1 Select
Recovered Clock#2 Select
Recovered Clock#3 Select
Global Reset
Global Configuration
SPE #1 Configuration
SPE #2 Configuration
SPE #3 Configuration
Bus Configuration
Global Performance Monitor Update
ISSUE 1
115
Register
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PM5366 TEMAP-84