PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 97

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
9.14 DS3/E3 HDLC Transmitters
PROPRIETARY AND CONFIDENTIAL
In each case, the DS3 transmitter drives the selected DS3 clock source onto the
TCLK output pins of the DS3/E3 line side interface.
The HDLC transmitter provides a serial data link for the DS3 C-bit parity path
maintenance data link, E3 G.832 Network Operator byte, E3 G.832 General
Purpose Communications Channel or E3 G.751 National Use bit. The HDLC
transmitter is used under microprocessor control to transmit HDLC data frames.
It performs all of the data serialization, CRC generation, zero-bit stuffing, as well
as flag, and abort sequence insertion. Upon completion of the message, a CRC-
CCITT frame check sequence (FCS) may be appended, followed by flags. If the
HDLC transmitter data FIFO underflows, an abort sequence is automatically
transmitted.
When enabled, the HDLC transmitter continuously transmits the flag sequence
(01111110) until data is ready to be transmitted.
The default procedure provides automatic transmission of data once a complete
packet is written. All complete packets of data will be transmitted. After the last
data byte of a packet, the CRC word (if CRC insertion has been enabled) and a
flag, or just a flag (if CRC insertion has not been enabled) is transmitted. The
HDLC transmitter then returns to the transmission of flag characters until the
next packet is available for transmission. While working in this mode, the user
must only be careful to avoid overfilling the FIFO; underruns cannot occur unless
the packet is greater than 128 bytes long. The HDLC transmitter will force
transmission if the FIFO is filled up regardless of whether or not the packet has
been completely written into the FIFO.
A second mechanism transmits data when the FIFO depth has reached a user
configured upper threshold. The HDLC transmitter will continue to transmit data
until the FIFO depth has fallen below the upper threshold and the transmission of
the last packet with data above the upper threshold has completed. In this
mode, the user must be careful to avoid overruns and underruns. An interrupt
can be generated once the FIFO depth has fallen below a user configured lower
threshold as an indicator for the user to write more data.
3.
Recovered DS3 clock from the RCLK[3:1] input pins. If the system
External jitter attenuation is recommended when using this DS3 timing
option.
interface is SBI, then TEMAP-84 is the SBI bus clock master, as in case
1 above. If the system interface is serial clock and data, TEMAP-84
derives TGAPCLK[3:1] from the recovered DS3 clock.)
ISSUE 1
85
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PM5366 TEMAP-84