PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 20

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
PROPRIETARY AND CONFIDENTIAL
• Extracts valid X-bits and indicates far end receive failure (FERF). The far end
• Accumulates up to 65,535 line code violation (LCV) events per second, 65,535
• Detects and validates bit-oriented codes in the C-bit parity far end alarm and
• Terminates the C-bit parity path maintenance data link with an integral HDLC
• Programmable pseudo-random test-sequence detection–(up to 2 32 -1 bit length
• Provides the overhead bit insertion for a DS3 stream.
• Provides a bit serial clock and data interface, and allows the M-frame boundary
• Provides B3ZS encoding.
• Generates an B3ZS encoded 100… repeating pattern to aid in pulse mask
• Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and
meets the ANSI T1M1.3 Section 7.1.2.4 requirement that AIS be detected in less
than 100 ms and is intended for non-BOC (Bell Operating Company)
applications.
receive failure status only changes if the two X-bits are the same. The status is
buffered for two M-frames, ensuring a better than 99.99% chance of freezing the
correct status for the duration of the out of frame occurrence.
P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per
second, 65,535 excessive zero (EXZ) events per second, and when enabled for
C-bit parity mode operation, up to 16,383 C-bit parity error events per second,
and 16,383 far end block error (FEBE) events per second (note that, over a one
second interval, only 9399 P-bit errors, C-bit parity errors, or FEBE events can
occur).
control channel.
receiver having a 128-byte deep FIFO buffer with programmable interrupt
threshold. Supports polled or interrupt-driven operation. Selectable none, one or
two address match detection on first byte of received packet.
patterns conforming to ITU-T O.151 standards) and analysis features.
Each one of three DS3 Transmit Sections:
and/or the overhead bit positions to be located via an external interface
testing.
the idle signal when enabled by internal register bits.
ISSUE 1
8
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PM5366 TEMAP-84