PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 164

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
12.2.2 SBI and Telecom Buses Both 77.76 MHz
PROPRIETARY AND CONFIDENTIAL
Restrictions on frame alignment pulses only exist when TVTs are supported.
The nature of the constraints depends on whether the VT pointer processors
(VTPPs) are bypassed:
The rising edge of LREFCLK must be aligned with a tolerance of +/- 5ns to the
rising edge of SREFCLK.
For reliable operation, the STM-1s used within the SBI and Telecom buses must
be aligned in time. To this end, one may manipulate the LSTM[1:0] and
SSTM[1:0] register bits and the position of the LAC1 and SDC1FP pulses. Table
15 summarizes the combinations.
Table 15
As an alternate formulation, if SSTM[1:0] and LSTM[1:0] were converted to their
decimal equivalents, one would have to satisfy the constraint:
SSTM[1:0]
(LSTM – SSTM) mod 4
00
01
10
11
• If the Egress VTPP is bypassed, the SAC1FP pulse must be
• If the Egress VTPP is not bypassed, the SAC1FP pulse must be 3n
• If the Ingress VTPP is bypassed, the LDC1J1V1 pulse must be
• If the Ingress VTPP is not bypassed, there is no restriction on the
precisely 13 SREFCLK cycles before the LAC1 pulse.
- 1 (where n = 0,1,2…) SREFCLK cycles before the LAC1 pulse.
precisely four SREFCLK cycles before the SDC1FP pulse.
alignment of SDC1FP and LDC1J1V1.
- 77.76 SBI and Telecom Bus Alignment Options
4n + 3
4n + 2
4n + 1
4n.
00
ISSUE 1
Clock Cycles LAC1 leads SDC1FP (n = 0, 1 , 2…)
= (Clock Cycles LAC1 leads SDC1FP) mod 4
4n + 1
4n + 3
4n + 2
01
4n
152
LSTM[1:0]
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
4n + 2
4n + 1
4n + 3
10
4n
AND M13 MULTIPLEXER
PM5366 TEMAP-84
4n + 3
4n + 2
4n + 1
11
4n