STE10-100A STMicroelectronics, STE10-100A Datasheet - Page 41

• Manufacturer Part Number: STE10-100A
• Description: Pci 10/100 Ethernet Controller With Integrated Phy
• Manufacturer: STMicroelectronics

STE10/100A
Table 8.
R/W* = Before writing the transmit and receive operations should be stopped.
CSR1 (offset = 08h), TDR - Transmit demand register
R/W* = Before writing the transmit process should be in the suspended state
CSR2 (offset = 10h), RDR - Receive demand register
R/W* = Before writing the receive process should be in the suspended state
CSR3 (offset = 18h), RDB - Receive descriptor base address
R/W* = Before writing the receive process should be stopped
CSR4 (offset = 20h), TDB - Transmit descriptor base address
R/W* = Before writing the transmit process should be stopped
31 ~ 0
31~ 0
31~ 2
31~ 2
6 ~ 2
Bit #
1, 0
1, 0
7
1
0
RPDM
Control/status register description (continued)
TPDM
RBND
Name
TBND
SWR
BAR
SAR
DSL
BLE
SAT
Big or little endian selection.
0: little endian (for example INTEL)
1: big endian (only for data buffer)
Descriptor skip length. Defines the gap between
two descriptors in the units of DW.
Bus arbitration
0: receive operations have higher priority
1: transmit operations have higher priority
Software reset
1: Reset all internal hardware (excluding
transceivers and configuration registers). This
signal will be cleared by the STE10/100A itself
after the reset process is completed.
Transmit poll demand.
While the STE10/100A is in the suspended
state, a write to this register (any value) will
trigger the read-tx-descriptor process, which
checks the own-bit; if set, the transmit process is
then started.
Receive poll demand.
While the STE10/100A is in the suspended
state, a write to this register (any value) will
trigger the read-rx-descriptor process, which
checks the own-bit, if set, the process to move
data from the FIFO to buffer is then started.
Start address of receive descriptor
Must be 00, DW boundary
Start address of transmit descriptor
Must be 00, DW boundary
Description
Registers and descriptors description
FFFFFFFFh
FFFFFFFFh
Default
00
00
0
0
0
0
0
0
RW type
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
RO
RO
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