STE10-100A STMicroelectronics, STE10-100A Datasheet - Page 57

• Manufacturer Part Number: STE10-100A
• Description: Pci 10/100 Ethernet Controller With Integrated Phy
• Manufacturer: STMicroelectronics

STE10/100A
Table 8.
CSR25 (offset = a4h), PAR0 - Physical address register 0 automatically recalled from EEPROM
CSR26 (offset = a8h), PAR1 - Physical address register 1 automatically recalled from EEPROM
For example, physical address = 00-00-e8-11-22-33 - PAR0= 11 e8 00 00 - PAR1= XX XX 33 22 - PAR0 and
CSR27 (offset = ach), MAR0 - Multicast address register 0
CSR28 (offset = b0h), MAR1 - Multicast address register 1
MAR0 and MAR1 are readable, but can be written only if the receive state is in stopped(CSR5 bit19-17=000)
31~24
23~16
31~24
23~16
31~24
23~16
31~24
23~16
15~8
15~8
15~8
15~8
Bit #
7~0
7~0
7~0
7~0
PAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bits 19-17=000).
Control/status register description (continued)
Name
MAB3
MAB2
MAB1
MAB0
MAB7
MAB6
MAB5
MAB4
PAB3
PAB2
PAB1
PAB0
PAB5
PAB4
---
---
Physical address byte 3
Physical address byte 2
Physical address byte 1
Physical address byte 0
Reserved
Reserved
Physical address byte 5
Physical address byte 4
Multicast address byte 3 (hash table 31:24)
Multicast address byte 2 (hash table 23:16)
Multicast address byte 1 (hash table 15:8)
Multicast address byte 0 (hash table 7:0)
Multicast address byte 7 (hash table 63:56)
Multicast address byte 6 (hash table 55:48)
Multicast address byte 5 (hash table 47:40)
Multicast address byte 4 (hash table 39:32)
Description
Registers and descriptors description
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
Default
From
From
From
From
From
From
00h
00h
00h
00h
00h
00h
00h
00h
RW type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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