STE10-100A STMicroelectronics, STE10-100A Datasheet - Page 46

• Manufacturer Part Number: STE10-100A
• Description: Pci 10/100 Ethernet Controller With Integrated Phy
• Manufacturer: STMicroelectronics

Registers and descriptors description
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Table 8.
CSR7 (offset = 38h), IER - Interrupt enable register
31~17
Bit #
16
15
14
13
12
11
10
9
8
7
6
5
4
3
RWTIE
TJTTIE
GPTIE
Control/status register description (continued)
FBEIE
Name
RCIE
RSIE
RUIE
TUIE
NIE
AIE
---
---
---
---
---
Reserved
Normal interrupt enable.
1: enables all the normal interrupt bits (see bit 16
of CSR5).
Abnormal interrupt enable.
1: enables all the abnormal interrupt bits (see bit
15 of CSR5).
Reserved
Fatal bus error interrupt enable.
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the fatal bus error interrupt.
Reserved
General purpose timer interrupt enable.
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the general purpose timer
expired interrupt.
Reserved
Receive watchdog time-out interrupt enable
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the receive watchdog time-out
interrupt.
Receive stopped interrupt enable.
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the receive stopped interrupt.
Receive descriptor unavailable interrupt enable.
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the receive descriptor
unavailable interrupt.
Receive completed interrupt enable.
1: this bit in conjunction with NIE (bit 16 of
CSR7) will enable the receive completed
interrupt.
Transmit under-flow interrupt enable.
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the transmit under-flow
interrupt.
Reserved
Transmit jabber timer time-out interrupt enable.
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the transmit jabber timer time-
out interrupt.
Description
Default
0
0
0
0
0
0
0
0
0
0
STE10/100A
RW type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W