STE10-100A STMicroelectronics, STE10-100A Datasheet - Page 47

• Manufacturer Part Number: STE10-100A
• Description: Pci 10/100 Ethernet Controller With Integrated Phy
• Manufacturer: STMicroelectronics

STE10/100A
Table 8.
CSR8 (offset = 40h), LPC - Lost packet counter
CSR9 (offset = 48h), SPR - Serial port register
31~17
31~15
15~0
10~4
Bit #
16
14
13
12
11
2
1
0
3
2
TDUIE
Control/status register description (continued)
TPSIE
Name
LPCO
TCIE
SWC
SDO
SRC
SRS
LPC
SDI
---
---
---
---
Transmit descriptor unavailable interrupt enable.
1: this bit in conjunction with NIE (bit 16 of
CSR7) will enable the transmit descriptor
unavailable interrupt.
Transmit processor stopped interrupt enable.
1: this bit in conjunction with AIE (bit 15 of
CSR7) will enable the transmit processor
stopped interrupt.
Transmit completed interrupt enable.
1: this bit in conjunction with NIE (bit 16 of
CSR7) will enable the transmit completed
interrupt.
Reserved
Lost packet counter overflow.
1: when lost packet counter overflow occurs.
Cleared after read.
Lost packet counter.
The counter is incremented whenever a packet
is discarded as a result of no host receive
descriptors being available. Cleared after read.
Reserved
Serial EEPROM read control.
When set, enables read access from EEPROM,
when SRS (CSR9 bit 11) is also set.
Serial EEPROM write control.
When set, enables write access to EEPROM,
when SRS (CSR9 bit 11) is also set.
Reserved
Serial EEPROM select.
When set, enables access to the serial
EEPROM (see description of CSR9 bit 14 and
CSR9 bit 13).
Reserved
Serial EEPROM data out.
This bit serially shifts data from the EEPROM to
the STE10/100A.
Serial EEPROM data in.
This bit serially shifts data from the STE10/100A
to the EEPROM.
Description
Registers and descriptors description
Default
0
0
0
0
0
0
0
0
1
1
RW type
RO/LH
RO/LH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
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