STE10-100A STMicroelectronics, STE10-100A Datasheet - Page 67

• Manufacturer Part Number: STE10-100A
• Description: Pci 10/100 Ethernet Controller With Integrated Phy
• Manufacturer: STMicroelectronics

STE10/100A
Table 12.
RDES1
RDES2
RDES3
31~26
23~22
21~11
10~ 0
31~0
31~0
Bit#
25
24
9
8
7
6
5
4
3
2
1
0
reserved Default = 0
Receive descriptor description (continued)
Name
RBS2
RBA1
RBA2
RBS1
RCH
RER
RW
CS
DB
CE
OF
FS
LS
FT
TL
---
---
First descriptor
Last descriptor
Packet too long (packet length > 1518 bytes). This bit is valid only in a
frame’s last descriptor.
Late collision. Set when collision is active after 64 bytes. This bit is valid only
in a frame’s last descriptor
Frame type. This bit is valid only in a frame’s last descriptor.
0: 802.3 type
1: Ethernet type
Receive watchdog (refer to CSR15, bit 4). This bit is valid only in a frame’s
last descriptor.
Dribble bit. This bit is valid only in a frame’s last descriptor
1: Packet length is not integer multiple of 8-bit
1: CRC error. This bit is valid only in a frame’s last descriptor
1: Overflow. This bit is valid only in a frame’s last descriptor
Reserved
Receive end of ring. Indicates this descriptor is last, return to base address
of descriptor
Second address chain
Used for chain structure, indicating the buffer 2 address is the next descriptor
address. Ring mode takes precedence over chained mode
Reserved
Buffer 2 size (DW boundary)
Buffer 1 size (DW boundary)
Receive buffer address 1. This buffer address should be double word
aligned.
Receive buffer address 2. This buffer address should be double word
aligned.
Description
Registers and descriptors description
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