RS8973 Mindspeed Technologies, RS8973 Datasheet
RS8973
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RS8973 Summary of contents
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... Bt8970 and Bt8960. The RS8973 is a highly integrated device that includes all of the active circuitry needed for a complete 2B1Q transceiver. In the receive portion of the device, a variable gain amplifier optimizes the signal level according to the dynamic range of the analog-to-digital converter ...
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... Ordering Information Model Number RS8973EPF Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products ...
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Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 3.0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3-1 3 ...
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... Conexant Preliminary Information RS8973 . . . . . . . . . . . . . . . . . . . . . . 3- 3-22 ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 4.3 Voltage Reference and Compensation Circuitry 4.4 Crystal/Clock Interface 5.0 Electrical and Mechanical Specifications 5.1 Absolute Maximum Ratings 5.2 Recommended Operating Conditions 5.3 Electrical Characteristics 5.4 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5 ...
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... Table of Contents viii Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver List of Figures Figure 1-1. HDSL T1/E1 Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Figure 1-2. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Figure 1-3. Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Figure 1-4 ...
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... List of Figures x Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver List of Tables Table 1-1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Table 1-2. Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Table 2-1. Symbol Source Selector/Scrambler Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Table 2-2. Four-Level Bit-to-Symbol Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Table 2-3 ...
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... List of Tables xii Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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... System Overview 1.1 Functional Summary The RS8973 High-bit-rate Digital Subscriber Line (HDSL) transceiver is an integral component of Conexant's HDSL chipset. System performance of the chipset allows 2-pair T1, 1-pair E1, 2-pair E1, and 3-pair E1 transmission. With its built-in frequency synthesizer, it can easily be configured through software for variable rate Symmetric DSL over Single Pair (SDSL) applications, using a single 10 ...
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... System Overview 1.1 Functional Summary The RS8973 comprises five major functions: a transmit section, a receive section, a timing recovery and clock interface, a microcomputer interface, and a test and diagnostic interface. between each of these functional blocks. Figure 1-2. Detailed Block Diagram Receive Section RXP RXN Digital VGA ...
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... Digitized receive data is passed to the digital signal processor (DSP) portion of the RS8973. After DC offset cancellation, the impulse shortening (IS) filter eliminates long tails caused by the line transformer. A replica of the transmit signal is subtracted from the total receive signal by a digital echo canceller. The ...
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... The serial monitor output can be viewed as a real-time virtual probe for looking at the transceiver’s internal signals. The programmable signal source is shifted out serially at 16 times the symbol rate. Most of the receive signal path is accessible through this output. 1-4 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 1.2 Pin Descriptions The RS8973 is packaged in a 100-pin plastic quad flat pack (PQFP). The pin assignments are shown in are listed in Figure 1-3. Pin Diagram VDD1 RD/DS WR/R/W ALE IRQ READY AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] DGND DGND VDD2 AD[7] MOTEL MUXED ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ...
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... NC DTEST3 VPLL – 71 TXP PGND – 72 VAA DTEST4 I 73 AGND AGND – 74 TXN AGND – 75 AGND Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver I/O Pin Pin Label I AGND – RXP IA – 78 RXN IA – 79 RXBP IA – 80 RXBN VAA – ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver Signal definitions are provided in column analog output OD = open-drain output analog input I/O = bidirectional connect Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name I/O MOTEL Motorola/Intel ALE Address Latch Enable CS Chip Select RD/DS Read/Data Strobe WR / R/W Write/ Read/Write ...
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... TQ0 = Don’t care (tie or pull up to supply rail) TDAT is sampled at the bit rate (two times the symbol rate) on the falling edge of BCLK. Runs at the symbol rate. It defines the data on the TQ and RQ interfaces. QCLK is also used to frame transmit/receive quats in serial mode. Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver N8973DSD ...
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... XTALI/MCLK, XTALO should be left floating. HCLK can be configured to run at 16, 32 times the symbol rate. Upon reset set to 16 times the symbol rate. This clock will be phase locked to the incoming data when the RS8973 is configured as the remote unit. Buffered-crystal oscillator output. Conexant Preliminary Information 1 ...
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... Dedicated ground pins for the digital circuitry. Must be held at same potential as AGND and PGND. Dedicated supply pins powering the analog circuitry. Dedicated ground pins for the analog circuitry. Must be held at the same potential as DGND and PGND. Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver N8973DSD ...
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... The reg_clk_en bit of Miscellaneous/Test Register (0x0F) is reset (0) on REG–R. The reg_clk_en bit of Miscellaneous/Test Register (0x0F) is set (1) on REG–C. In this mode, the internal clock synthesizer is bypassed. N8973DSD shows the interconnection between two RS8973s for a single loop REG–C RS8973 Bt8953A/ RS8953B ...
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... System Overview 1.3 Regenerator Configuration 1-12 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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Functional Description 2.1 Transmit Section The transmit section block diagram is shown in major functions: a symbol source selector/scrambler, a variable gain digital-to-analog converter (DAC), a pulse-shaping filter, an analog CT reconstruction filter, and a line driver. Figure 2-1. ...
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... The bit stream is converted into symbols for the four-level cases, as shown in Table 2-2. Table 2-2. Four-Level Bit-to-Symbol Conversions 2-2 Symbol Source Selector/Scrambler Mode First Input Bit Second Input Bit (Sign) (Magnitude Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver Table 2-1. Output Symbol – 3 – N8973DSD ...
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... NOTE: 2.1.2 Variable Gain Digital-to-Analog Converter A four-level DAC is integrated into the RS8973 to convert the output of the symbol source to analog form. The normalized values of these four analog levels are + – 1 and – 3. Each represents a symbol, or quat. To provide precise adjustment of transmitted power, the level of the DAC can be adjusted. The Transmitter Gain Register [tx_gain ...
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... The analog CT reconstruction filter removes the discrete-time images from the transmit signal before it is amplified by the line driver. 2.1.5 Line Driver The line driver buffers the output of the CT reconstruction filter to drive diverse loads. The output of the line driver is differential. 2-4 Single-Chip SDSL/HDSL Transceiver Specifications. Conexant Preliminary Information RS8973 N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 2.2 Receive Section Like the transmit section, the receive section consists of both analog and digital circuitry. The VGA provides the interface to the analog signals received from the line and the hybrid. The ADC then digitizes the analog signal so it can be further processed in the DSP section of the receiver ...
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... Figure 2-3. Receiver Digital Signal Processing SLM IS Digital Front-End FILTER – – LEC Echo Canceller 2-6 Figure 2-3 Detector FELM DAGC FFE – NEC Transmit Symbol Equalizer Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver shows the interconnections and – PKD Channel Unit Interface Slicer – – EP DFE N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 2.2.3.1 Digital Prior to the main signal processing, the input signal must be adjusted for any DC Front-End offset. The front-end module also monitors the input signal level, which includes measuring DC and AC input signal levels, detecting and counting overflows, and detecting alarms based on the far-end signal level. ...
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... Interrupt Mask Register High [mask_high_reg; 0x03]. 2.2.4 Impulse Shortening Filter The impulse shortening (IS) filter is a high pass filter which pre-equalizes the channel and eliminates long tails caused by the transformer. 2-8 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 2.2.5 Echo Canceller The echo canceller (EC) removes images of the transmitted symbols from the received signal and consists of two blocks: a linear and nonlinear echo canceller. The organization of the blocks is displayed in Processing. 2.2.5.1 Linear Echo The linear echo canceller (LEC conventional LMS, finite impulse response ...
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... If neither of the peaked conditions exist, the output of the slicer is used. 2.2.7.3 Error Signals The detector computes two error signals for use in the equalizer: a 16-bit slicer and a 16-bit equalizer. 2-10 coefficients. Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 2.2.7.4 Scrambler The scrambler can operate as either a scrambler descrambler. The Module scrambler block is used during the scrambled-1s part of the start-up sequence. This provides an error-free signal for equalizer adaptation. This scrambler is essentially a 23-bit-long Linear Feedback Shift Register (LFSR). The feedback point depends on whether the transceiver is being used in a central-office or remote-terminal application ...
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... MSBs of the accumulator are compared against the SNR Alarm Threshold Register [snr_alarm_th_low, snr_alarm_th_high; 0x34, 0x35]. If the result is greater than this threshold, an interrupt is set in the irq_source register. The threshold is set through the MCI. 2-12 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 2.3 Timing Recovery and Clock Interface The timing recovery and clock interface block consists of the timing recovery circuit, the crystal amplifier, and the clock synthesizer, as detailed in The main purpose of this circuitry is to generate the internal clocks, including BCLK and QCLK, from the 10.24 MHz input MCLK, based on the selected data rate, and to recover the clock from received data ...
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... Figure 2-5. Timing Recovery and Clock Interface Block Diagram 2-14 Single-Chip SDSL/HDSL Transceiver Phase Detector Control Meter Register Registers [0x40, 0x41] Detected Timing Symbol Recovery Circuit Equalizer Error Clock Synthesizer Crystal Amplifier XTALI (40) Y1 C10 (For all data rates) Conexant Preliminary Information RS8973 QCLK (87) HCLK (35) XOUT (36) XTALO (39) C11 Y1 = 10.24 MHz N8973DSD ...
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... PLL Frequency Register [pll_frequency_low, pll_frequency_high; 0x5E, 0x5F]. 2.3.2 Crystal Amplifier The crystal amplifier reduces the support circuitry needed for the RS8973 by eliminating the need for an external crystal oscillator (XO). A crystal of 10.24 MHz frequency can be connected directly to the XTALI and XTALO pins. ...
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... Figure 2-7. Parallel Master Mode RQ[1]/TQ[1] RQ[0]/TQ[0] 2-16 BCLK QCLK RDAT Sign Magnitude Sign Sign Magnitude Sign TDAT Figure 2-7. QCLK Sign Sign 0 Magnitude Magnitude 0 Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver Figure 2-6. Magnitude Sign 1 2 Magnitude Sign 1 2 Sign 1 2 Magnitude 1 2 N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver The parallel slave mode uses RBCLK and TBCLK inputs to synchronize data transfer. RBCLK and TBCLK must be frequency-locked to QCLK, though the use of two internal FIFOs allows an arbitrary phase relationship to QCLK. TQ[1] and TQ[0] are sampled on the active edge of TBCLK, as programmed through the MCI ...
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... MOTEL high selects Motorola-type microcomputer and uses control • MUXED high configures the interface to use the multiplexed address-data • The READY pin is provided to indicate when the RS8973 is ready to The MCI provides access to a 256-byte internal address space. The registers in this address space provide configuration, control, status, and monitoring capabilities ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 2.5.2.1 RAM Access The internal RAM of the scratch pad, LEC, NEC, DFE, equalizer, and microcode Registers are accessed indirectly. They all share a common data register which is used for both read and write operations: Access Data Register [access_data_byte[3:0]; [0x7C–0x7F]. Each RAM has an individual read select and write select register. ...
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... Write operations to undefined registers have unpredictable effects. Read operations from undefined registers have undefined results. 2.5.6 Timers Eight timers are integrated into the RS8973 to control the various on-chip meters and to aid the microcomputer in stepping through the events of the start-up sequence. ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver Table 2-6. Timers Startup Timer 1 Startup Timer 2 Startup Timer 3 Startup Timer 4 SNR Alarm Timer General Purpose Timer 3 General Purpose Timer 4 Four timers are provided for use in timing start-up events. These timers share a single prescaler, which divides the symbol clock by 1024 and supplies this slow clock to the four counters ...
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... JTAG controllers. Refer to the IEEE Std 1149.1 specification for details concerning the Instruction Register and JTAG state machine. A Boundary Scan Description Language (BSDL) file for the RS8973 is also available from the factory upon request. Table 2-7. JTAG Device Identification Register ...
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Registers 3.1 Conventions Unless otherwise noted, the following conventions apply to all applicable register descriptions: • For storage of multiple-bit data fields within a single byte-wide register, • If only a single data field is stored in a byte-wide ...
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... Registers 3.2 Register Summary 3-2 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver N8973DSD Conexant Preliminary Information 3.0 Registers 3.2 Register Summary 3-3 ...
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... Registers 3.2 Register Summary 3-4 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver N8973DSD Conexant Preliminary Information 3.0 Registers 3.2 Register Summary 3-5 ...
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... Registers 3.2 Register Summary 3-6 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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... Smaller values represent earlier versions, while larger values represent later versions. The zero value represents the original prototype release. Consult factory for current values and revision. Part ID—Read-only binary field set to binary 011, identifying the part as RS8973. part_id[2:0] The following table shows Part IDs for different DSL transceivers: ...
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... Digital front-end output/IS input 11 0001 Linear echo replica 11 0010 DFE subtractor output 11 0011 EP subtractor output/slicer input 11 0100 Timing recovery phase detector output/loop filter input 11 0101 Timing recovery loop filter output/frequency synthesizer input Conexant Preliminary Information RS8973 smon[1] smon[0] ) × 16. QCLK Source N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 0x02—Interrupt Mask Register Low (mask_low_reg) Independent read/write mask bits for each of the Timer Source Register [timer_source; 0x04] interrupt flags. A logical 1 represents the masked condition. A logical 0 represents the unmasked condition. All mask bits behave identically with respect to their corresponding interrupt flags. Setting a mask bit prevents the corresponding interrupt flag from affecting the IRQ output ...
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... Signal-to-Noise Ratio Low Alarm—Active when the SNR Alarm meter value is greater than low_snr the threshold stored in the SNR Alarm Threshold Registers [snr_alarm_th_low, snr_alarm_th_high; 0x34–0x35]. 3-10 Single-Chip SDSL/HDSL Transceiver meter sut4 sut3 — sync high_felm Conexant Preliminary Information RS8973 1 0 sut2 sut1 1 0 low_felm low_snr N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 0x06—Channel Unit Interface Modes Register (cu_interface_modes — — — Transmit Baud Clock Polarity—Read/write control bit defines the polarity of the TBCLK tbclk_pol input while in the parallel slave interface mode. When tbclk_pol is set, TQ[1,0] is sampled on the falling edge of TBCLK; when cleared, TQ[1,0] is sampled on the rising edge. ...
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... Adaptation Gain—Read/write binary field which specifies the adaptation gain. adapt_gain[1,0] adapt_gain[1,0] 3- imp_short[0] rphs[3] rphs[ adapt_ zero_coefficients zero_output coefficients Normalized Gain 512 Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver rphs[1] rphs[ adapt_gain[1] adapt_gain[0] N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 0x09—Nonlinear Echo Canceller Modes Register (nonlinear_ec_modes negate_symbol symbol_delay[2] symbol_delay[1] symbol_delay[0] Negate Symbol—Read/write control bit which, when set, inverts (2s complement) the receive negate_symbol signal path at the output of the nonlinear echo canceller. When cleared, the signal path is unaffected. This function is independent of all other NEC mode settings. Symbol Delay— ...
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... Valid output levels are limited – transmitter_off htur_lfsr data_source[2] Output Pulse Level 00 – – – 23 – when cleared, it selects the local unit (HTU-C/LT – Transmitter Mode Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver data_source[1] data_source[0] N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 0x0C—Timer Restart Register (timer_restart) Independent read/write restart bits, one for each of the eight internal timers. Setting an individual bit causes the associated timer to be reloaded with the contents of its interval register. For the four symbol-rate timers (meter, snr, t3, t4), reloading occurs within 1 symbol period. For the four start-up timers (sut1– ...
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... Normally this bit is reset and ÷ Configuration. Requirements, and Characteristics, for MCI timing requirements and switching Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver sut3 sut2 sut1 0x0D—Timer Enable Register res[2] res[1] async_mode ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 0x14, 0x15—Startup Timer 3 Interval Register (sut3_low, sut3_high) A 2-byte read/write register that stores the countdown interval for Startup Timer 3 in unsigned binary format. Each increment represents 1024 symbol periods. The contents of this register are automatically loaded into its associated timer after the timer_restart bit is set, or after the timer counts down to zero while in the continuous mode ...
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... Data Rate Range 800 to 1200 kbps Less than 800 kbps Above 1200 kbps Reserved Function Normal Operation (Loopback Disabled) Hybrid Inputs Disabled (RXBP, RXBN) Transmitting Loopback Silent Loopback Conexant Preliminary Information RS8973 1 0 clk_freq[1] clk_freq[ gain[1] gain[0] N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver Switch Cap Pole Control—Read/write control bit, specifies the pulse shaping filter switch_cap_pole characteristics. When switch_cap_pole is set, it enables output pulse shape conforming to ETSI specifications for 2320 kbps operation. When reset, it enables output pulse shape for other data rates. ...
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... The value of the Transmit Calibration Register is set during manufacturing testing by Conexant, and corresponds to the value required to operate the RS8973 at a nominal 13.5 dBm transmit power, assuming the recommended transformer coupling/hybrid circuit is used. Users can override this calibration by writing their own value into the Transmitter Gain Register [tx_gain ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 0x29—Transmitter Gain Register (tx_gain — — tx_gain[3] Transmit Gain—A 4-bit, 2s-complement, read/write field controlling the transmitter gain. tx_gain[3:0] Upon initialization, the value in the Transmitter Calibration Register [tx_calibrate; 0x28] can be written into this register by software, to set the transmitter gain to the nominal value. ...
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... DAGC function. The difference is used as the error input to the DAGC while in the self-adaptation mode. In the DAGC’s equalizer-error adaptation mode, the contents of this register are not used. 3-22 Single-Chip SDSL/HDSL Transceiver D[4] D[3] D[2] Conexant Preliminary Information RS8973 1 0 D[1] D[0] N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 0x3A—Symbol Detector Modes Register (detector_modes enable_peak_ output_mux_ output_mux_ detector control[1] control[0] enable_peak_ Enable Peak Detector—Read/write control bit that enables the peak detection function when detector set; disables the function when cleared. When enabled, the peak detector output overrides the slicer output if the peak detection criteria are met ...
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... FFE delays are not fixed, but result from the microprogrammed implementation of these functions. The value should be set according to software supplied by Conexant — — — 3-24 Single-Chip SDSL/HDSL Transceiver – 23 – 1); when cleared, it selects the local unit – 23 – 1 — D[3] D[2] Conexant Preliminary Information RS8973 1 0 D[1] D[0] N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 0x3C—Digital AGC Modes Register (dagc_modes — — — eq_error_ Equalizer Error Adaptation—Read/write control bit that selects between the equalizer-error adaptation adaptation mode when set, and the self-adaptation mode when cleared. Equalizer error adaptation uses the equalizer error signal produced by the slicer as the DAGC error input signal. In self-adaptation, the value of the DAGC Target Register [dagc_target_low, dagc_target_high ...
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... ADC overflow conditions which occur during each meter timer countdown interval, limited to a maximum count of 255 (0xFF). The meter register is automatically loaded at the end of each countdown interval D[7] D[6] D[5] 3-26 Single-Chip SDSL/HDSL Transceiver — zero_output zero_coefficients D[14] D[13] D[12] D[22] D[21] D[20 D[4] D[3] D[2] Conexant Preliminary Information RS8973 1 0 adapt_ adapt_gain coefficients 1 0 D[11] D[10] D[19] D[18 D[1] D[0] N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 0x44, 0x45—DC Level Meter Register (dc_meter_low, dc_meter_high) A 2-byte read-only register containing the 16 MSBs of the 32-bit, 2s-complement DC-level meter accumulator. This meter sums the value of the receive signal input path—after DC offset correction but before echo cancellation—over each Meter Timer countdown interval. Automatically loaded at the end of each interval, the meter register must be read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5F) ...
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... This meter counts the number – 1 symbols detected during each Meter Timer countdown interval. No increment occurs when – 3 symbol is detected. The meter register is automatically loaded at the end of each countdown interval D[7] D[6] D[5] 3-28 Single-Chip SDSL/HDSL Transceiver D[4] D[3] D[2] D[12] D[11] D[10 D[4] D[3] D[2] D[12] D[11] D[10 D[4] D[3] D[2] Conexant Preliminary Information RS8973 1 0 D[1] D[0] D[9] D[ D[1] D[0] D[9] D[ D[1] D[0] N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 0x50, 0x51—Noise Level Meter Register (nlm_low, nlm_high) A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned noise-level meter accumulator. This meter sums the absolute value of the detector’s slicer-error signal over each Meter Timer countdown interval. Automatically loaded at the end of each interval, the meter register must be read the low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5F) ...
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... DFE coefficient within 2 symbol periods. Does not affect the value of the access data register — D[6] D[5] 3-30 Single-Chip SDSL/HDSL Transceiver D[4] D[3] D[ D[4] D[3] D[ D[4] D[3] D[ D[4] D[3] D[2] Conexant Preliminary Information RS8973 1 0 D[1] D[ D[1] D[ D[1] D[ D[1] D[0] N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 0x76—Scratch Pad Read Tap Select (sp_tap_select_read) A 6-bit read/write register representing an unsigned binary address defined over a range decimal. When written, this register causes the selected 8-bit scratch pad memory location to be subsequently loaded into the lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within 2 symbol periods. ...
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... FFE Data Taps 0–7 EP Coefficients 0–4 EP Data Taps 0–4 DAGC Gain—Least-Significant Word DAGC Gain—Most-Significant Word DAGC Output FFE Output DAGC Input FFE Output, Delayed 1 Symbol Period DAGC Error Signal Equalizer Error Signal Slicer Error Signal Reserved Conexant Preliminary Information RS8973 1 0 D[1] D[0] N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 0x79—Equalizer Write Select Register (eq_add_write) A 6-bit read/write register representing an unsigned binary address defined over a range decimal. When written, this register causes the lowest-order 16 bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F subsequently written to the selected equalizer register file location within 2 symbol periods. ...
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... Registers 3.3 Register Description 3-34 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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... Four types of interconnections are discussed N8973DSD 4 This section replaces the RS8973 Application Note (N8973AN1A). Transmission line interface, including the compromise hybrid DC blocking capacitor Voltage reference and compensation circuitry Crystal/clock interface Conexant Preliminary Information 4-1 ...
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... Single-Chip SDSL/HDSL Transceiver Diagram, illustrates the interconnections 15.4 Surge Protection Matching Resistors 15.4 Surge Protection Secondary Compromise Hybrid Circuit Conexant Preliminary Information RS8973 Figure 4-1, Line Interface Line Transformer L 1:2 Line Surge C10 Protection Primary R11 R12 N8973DSD ...
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... NPO ceramic capacitors because of their highly linear characteristics. Although the RS8973 contains a digital echo canceller (EC), the hybrid is needed to reduce the signal level input to the ADC. This eliminates ADC overflow for short loops and increases the resolution of the digitized receive signal for better digital signal processing performance ...
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... The primary inductance (L) of the transformer (line side very critical parameter too high, the cutoff frequency of the filter will be too low and the RS8973 Echo Canceller and Equalizer will not be able to cancel out the low frequency components of the echo and inter-symbol interference ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver Table 4-3. Line Transformer Specifications Parameter (1) Turns Ratio Primary Inductance Return Loss (mid-band) Return Loss (low-band) Return Loss (high-band) Longitudinal Balance (low-band) Longitudinal Balance (high band) Insertion Loss Frequency Response Total Harmonic Distortion NOTE(S): (1) Turns ratio is specified line side to circuit side (line side:circuit side). The line side windings are usually split to accommodate a DC blocking capacitor ...
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... Table 4-7. Compensation Capacitor Values In addition to the compensation capacitors, an external resistor is needed to set the bias current used in the RS8973. This resistor must be connected between the RBIAS pin (pin 56) and analog ground. The recommended value of the resistor is given in Table 4-8. Bias Current Resistor Value ...
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... Single-Chip SDSL/HDSL Transceiver 4.4 Crystal/Clock Interface A crystal or an external clock is needed to provide a reference clock for the RS8973 crystal is used, it must be connected to the XTALI/MCLK and XTALO pins along with two external capacitors as shown in recommended specification for the crystal is given in vendors and their associated part numbers is displayed external clock is used, it must be connected to the XTALI/MCLK pin (pin 40), and the XTALO pin (pin 39) must be left floating ...
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... Interconnection Information 4.4 Crystal/Clock Interface 4-8 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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Electrical and Mechanical Specifications 5.1 Absolute Maximum Ratings Stresses above those listed in device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those listed in the operational sections of ...
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... Capacitive loading over which all digital output switching characteristics are guaranteed. (3) Still-air temperature range over which all electrical characteristics and timing requirements/characteristics are guaranteed. 5-2 Minimum 3.0 4.75 4.75 4.75 2.0 –0.3 0.9 × V DD2 –0.3 (2) — –40 (3) Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver Table 5-2. Typical Maximum Units 3.3 3.6 V 5.0 5.25 V 5.0 5.25 V 5.0 5.25 V — ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 5.3 Electrical Characteristics Typical characteristics measured at nominal operating conditions: • T • V • V Minimum/maximum characteristics guaranteed over extreme operating conditions: • Min • Min The parameters of the electrical characteristics are displayed in N8973DSD 5.0 Electrical and Mechanical Specifications = 25 ° 3.3 V DD1 = 5 ...
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... Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver Typical Maximum Units — — V — 0.4 V — 0.4 V — — — –400 A 100 TBD mA 101 TBD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 5.4 Clock Timing Tables 5-4 characteristics. clock control timing, respectively. Table 5-4. MCLK Timing Requirements Symbol Parameter 1 MCLK Period (1) 2 MCLK Pulse-Width Low 3 MCLK Pulse-Width High NOTE(S): ( external clock is applied to XTALI/MCLK referred to as MCLK. Max tolerance = ± 32 ppm. ...
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... The symbol rate is data rate ÷ 2. QCLK Figure 5-2. Clock Control Timing 4,5,6 7 HCLK QCLK 5-6 Single-Chip SDSL/HDSL Transceiver Minimum — – 20 QCLK T 2 – 20 QCLK –20 — Conexant Preliminary Information RS8973 Maximum Units — QCLK QCLK N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 5.5 Channel Unit Interface Timing Tables 5-7 switching characteristics. timing in parallel master mode, parallel slave mode, and serial mode, respectively. Table 5-7. Channel Unit Interface Timing Requirements, Parallel Master Mode Symbol 14 TQ[1,0] setup prior to QCLK falling edge 15 TQ[1,0] hold after QCLK low Table 5-8 ...
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... Figure 5-4. Channel Unit Interface Timing, Parallel Slave Mode RBCLK RQ[1:0] TBCLK TQ[1:0] 5-8 Single-Chip SDSL/HDSL Transceiver Parameter (2) (2) Parameter (1) ( Conexant Preliminary Information RS8973 Minimum Maximum Units T T — QCLK QCLK T 4 — — QCLK T 4 — — QCLK 25 — — ns ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver Figure 5-4. Channel Unit Interface Timing, Parallel Slave Mode TBCLK and RBCLK polarities are programmable through the CU Interface Modes Register. The figure depicts both NOTE(S): clocks programmed to falling-edge active. Table 5-11. Channel Unit Interface Timing Requirements, Serial Mode Symbol ...
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... Electrical and Mechanical Specifications 5.5 Channel Unit Interface Timing Figure 5-5. Channel Unit Interface Timing, Serial Mode HCLK 31 30 BCLK 33 32 QCLK RDAT 25 TDAT 5-10 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 29 N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 5.6 Microcomputer Interface Timing Tables 5-13 and switching characteristics, respectively. write and read timing. Table 5-13. Microcomputer Interface Timing Requirements Symbol Parameter 34 ALE pulse-width high 35 Address setup prior to ALE falling edge 36 (1) Address hold after ALE low 37 ALE low prior to Write Strobe falling edge 38a Read Strobe falling edge after ALE falling edge – ...
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... Write Strobe pulse-width (symbol 39) should meet the synchronous mode timing requirements for a symbol rate of 640 kbps (74 nx), which is the power-on default. 5-12 Minimum (1) (1, 7) (1) (1) (2,3) (2,3) (3,4) (3,5) (3,6) (3) (3) (1) (1) Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver Maximum Units 2 — ns — T ÷ QCLK 2 — ns — — ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver Figure 5-6. MCI Write Timing, Intel Mode (MOTEL = 0) AD[7:0] Address or ADDR[7: Write Strobe 34 ALE READY N8973DSD 5.0 Electrical and Mechanical Specifications Data (Input Conexant Preliminary Information 5.6 Microcomputer Interface Timing 45 5-13 ...
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... ADDR[7: Write Strobe R/W 34 ALE READY Figure 5-8. MCI Read Timing, Intel Mode (MOTEL = 0) AD[7:0] Address or ADDR[7: Read Strobe 34 ALE READY 5-14 Single-Chip SDSL/HDSL Transceiver Data (Input Data (Output Conexant Preliminary Information RS8973 45 46 N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver Figure 5-9. MCI Read Timing, Motorola Mode (MOTEL = 1) AD[7:0] Address or ADDR[7: Read Strobe R/W 34 ALE READY N8973DSD 5.0 Electrical and Mechanical Specifications Data (Output Conexant Preliminary Information 5.6 Microcomputer Interface Timing 52 46 5-15 ...
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... Electrical and Mechanical Specifications 5.6 Microcomputer Interface Timing Figure 5-10. Internal Write Timing Write Strobe IRQ Internal Register Internal RAM Access Data Register 5-16 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 5.7 Test and Diagnostic Interface Timing Tables 5-15 switching characteristics. SMON timing, respectively. Table 5-15. Test and Diagnostic Interface Timing Requirements Symbol 63 TCK pulse-width high 64 TCK pulse-width low 65 TMS, TDI setup prior to TCK rising edge 66 (1) TMS, TDI hold after TCK high NOTE(S): (1) Also applies to functional inputs for SAMPLE/PRELOAD and EXTEST instructions ...
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... HCLK must be programmed to operate at 16 times the symbol rate (16 × F Figure 5-11. JTAG Interface Timing TDO 69 TCK 65 TDI TMS Figure 5-12. SMON Timing HCLK 72 71 SMON 5-18 Parameter (1) (1) (2) ). QCLK Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver Minimum Maximum Units 0 — ns — — ns — — ns — N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver 5.8 Analog Specifications Tables 5-17 specifications. two- and three-pair systems. template for one-pair systems. bound of the average PSD of 392, 584, and 1160 kbaud systems, respectively. Table 5-17. Receiver Requirements and Specifications Parameter Input signals Input voltage range Input resistance Input resistance ...
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... R = 135 , calibrated gain 13.4 QCLK L — — — , for the test circuit 2, 784 kbps 1168 kbps 1,25T – 0,16 14T Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver Typ Max Units — — — — 14 dBm 0.20 — dB VAA/2 — V — ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver Table 5-19. Transmit Pulse Template for Two- and Three-Pair Systems (Source ETSI TS 101 135 Formerly ETR 152) Normalized Level A 0.01 0.0264 B 1.07 2.8248 C 1.00 2.6400 D 0.93 2.4552 E 0.03 0.0792 F –0.01 –0.0264 G –0.16 –0.4224 H –0.05 –0.1320 N8973DSD 5.0 Electrical and Mechanical Specifications ...
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... G = – 0,20 14T Quaternary Symbols + 0.0083 V 0.8917 V 0.8333 V 0.7750 V 0.0333 V –0.0083 V –0.1667 V –0.0417 V Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver – 0, – 0,05 50T – 1 – 3 –0.0083 V –0.0250 V –0.8917 V –2.6750 V –0.8333 V –2.5000 V – ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver Figure 5-15. Upper Bound of the Average PSD of a 392 kbaud System (Source ETSI TS 101 135 Formerly ETR 152) dBm/Hz – 20 – 40 – 60 – 80 – 100 – 120 1 e3 Figure 5-16. Upper Bound of the Average PSD of a 584 kbaud System (Source ETSI TS 101 135 Formerly ETR 152) dBm/Hz – ...
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... Figure 5-18. Transmitter Test Circuit RS8973 + Line Driver – 5-24 Single-Chip SDSL/HDSL Transceiver 1 4, shows the transmitter test circuit. Figures 5-19 15.4 1:2 TXP (71) Line Transformer 15.4 TXP (74) Primary Inductance = 2mH Conexant Preliminary Information RS8973 Hz 4, and 5-20 show the + + R L – – N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver Figure 5-19. Standard Output Load (Totem Pole and Three-State Outputs) Figure 5-20. Open-Drain Output Load (IRQ) N8973DSD 5.0 Electrical and Mechanical Specifications IOL From RS8973 CL IOH I OD From RS8973 C L Conexant Preliminary Information 5.9 Test Conditions 1 DD2 5-25 ...
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... Figure 5-22. Output Waveforms for Timing Tests VDD 2.4 V Output High 5-26 Single-Chip SDSL/HDSL Transceiver shows the input waveforms. Figures 5-22 2 Input Input Input Low Low High 0 Output Output Low Low Conexant Preliminary Information RS8973 and 5-23 show the output Output High N8973DSD ...
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... RS8973 Single-Chip SDSL/HDSL Transceiver Figure 5-23. Output Waveforms for Three-state Enable and Disable Tests 1.5 V Output Disabled N8973DSD 5.0 Electrical and Mechanical Specifications V – 0 1 Output Output Disabled Enabled Conexant Preliminary Information 5.10 Timing Measurements 5-27 ...
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... Electrical and Mechanical Specifications 5.11 Mechanical Specifications 5.11 Mechanical Specifications Figure 5-24. 100-Pin PQFP TOP VIEW 5-28 Single-Chip SDSL/HDSL Transceiver BOTTOM VIEW 1.60 REF. (.063) Conexant Preliminary Information RS8973 ALL DIMENSIONS IN M MILLIMETERS MIN. NOM. MAX. A ---- 3.04 3. 0.25 0.33 ---- A 2 2.57 2.71 2.87 D 23.20 BSC. ...
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Appendix A: Acronym List The following list of acronyms and abbreviations does not include all signal, register, and bit names. N8973DSD A A ADC analog-to-digital converter AGC automatic gain control B BDSL Boundary Scan Description Language BER bit error rate ...
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... Symmetric Digital Subscriber Line over Single Pair SLM Signal Level Meter SMON serial monitor SNR signal-to-noise ratio T TAP test access port TCK test clock TMS test mode select V VGA variable gain amplifier X XO crystal oscillator Conexant Preliminary Information RS8973 Single-Chip SDSL/HDSL Transceiver N8973DSD ...
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Further Information Hong Kong literature@conexant.com Phone: (852) 2827 0181 1-800-854-8099 (North America) Fax: (852) 2827 6488 33-14-906-3980 (International) India Web Site Phone: (91 11) 692 4780 www.conexant.com Fax: (91 11) 692 4712 World Headquarters Korea Conexant Systems, Inc. Phone: (82 ...