RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 99

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
Table 5-13. Microcomputer Interface Timing Requirements
N8973DSD
NOTE(S):
(1) Address is defined as AD[7:0] when MUXED = 1, and ADDR[7:0] when MUXED = 0.
(2) In Intel mode, Write Strobe is defined as WR and CS asserted. In Motorola mode, it is defined as DS and CS asserted when R/W
(3) In Intel mode, Read Strobe is defined as RD and CS asserted. In Motorola mode, it is defined as DS and CS asserted when R/W
(4) The timing listed is for the synchronous mode of the MCI, which is power-on default. It can also be set to asynchronous mode
Symbol
38b
38a
34
35
36
37
39
40
41
42
43
44
45
46
47
48
is low.
is high.
by setting bit 0 of the miscellaneous/test register (address 0x0F) to a 1. In this case, the minimum timing changes to 40 ns for
symbol 39, and 50 ns for symbols 40 and 50. Synchronous mode is preferred because it reduces switching noise. To switch to
asynchronous mode, the Write Strobe pulse-width (symbol 39) should meet the synchronous mode timing requirements for a
symbol rate of 640 kbps (74 nx), which is the power-on default.
ALE pulse-width high
Address setup prior to ALE falling edge
Address hold after ALE low
ALE low prior to Write Strobe falling edge
Read Strobe falling edge after ALE falling edge – muxed mode
(MUXED = 1)
(MUXED = 0)
Write Strobe pulse-width low
Read Strobe pulse-width low
Data In setup prior to Write Strobe rising edge
Data In hold after Write Strobe high
R/W setup prior to Read/Write Strobe falling edge
R/W hold after Read/Write Strobe high
ALE falling edge after Write Strobe high
ALE falling edge after Read Strobe high
RST pulse-width low
Write Strobe rising edge after READY low
Read Strobe falling edge after ALE falling edge – non-muxed mode
(3)
(3)
5.6 Microcomputer Interface Timing
Tables 5-13
and switching characteristics, respectively.
write and read timing.
(1)
Parameter
(3,4)
(2,4)
(2)
and
(1)
Preliminary Information
(2)
5-14
(2)
Conexant
list microcomputer interface (MCI) timing requirements
Figure 5-10
illustrates internal write timing.
5.0 Electrical and Mechanical Specifications
T
T
QCLK
QCLK
Figures 5-6
Minimum
÷ 32 + 25
÷ 32 + 25
30
10
20
20
30
10
10
20
20
50
5
1
5
0
5.6 Microcomputer Interface Timing
through
Maximum
5-9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
illustrate MCI
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5-11