RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 23

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
Figure 1-4. Regenerator System Block Diagram
N8973DSD
To COT
REG–R
RS8973
XTALO (39)
10.24 MHz
XTALI/MCLK (40)
1.3 Regenerator Configuration
Figure 1-4
regenerator system. Bt8953A/RS8953B provides an internal cross-connect data
path between REG-R and REG-C.
the power-on default.
REG–R.
REG–C. In this mode, the internal clock synthesizer is bypassed.
HCLK on REG–R is configured to run at 16 times the symbol rate, which is
The reg_clk_en bit of Miscellaneous/Test Register (0x0F) is reset (0) on
The reg_clk_en bit of Miscellaneous/Test Register (0x0F) is set (1) on
HCLK (35)
shows the interconnection between two RS8973s for a single loop
Preliminary Information
Conexant
RS8953B
Bt8953A/
REG–C
RS8973
XTALO (39)
NC
XTALI/MCLK (40)
1.3 Regenerator Configuration
HCLK (35)
1.0 System Overview
To RT
1-11