S1D13700F01 Epson Electronics America, Inc., S1D13700F01 Datasheet - Page 17

• Manufacturer Part Number: S1D13700F01
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 2005/12/13
Pin Name Type Pin #
SCANEN
RESET#
TSTEN
WAIT#
WR#
CS#
AS#
O
I
I
I
I
I
I
42
43
54
61
36
37
38
HTB2T
CID1
Cell
T1
SI
SI
CI
SI
HIOVDD
HIOVDD
HIOVDD
HIOVDD
HIOVDD
HIOVDD
HIOVDD
Table 5-2 Host Interface Pin Descriptions
Power
RESET#
Power
State
On
—
—
—
—
—
—
Z
Revision 4.05
This input pin has multiple functions.
Chip select.
This active-low input enables the S1D13700F01. It is usually
connected to the output of an address decoder device that maps
the S1D13700F01 into the memory space of the controlling
microprocessor.
This output pin has multiple functions.
This input pin has multiple functions.
This active-low input performs a hardware reset of the
S1D13700F01 which sets all internal registers to their default
states and forces all signals to their inactive states.
Note: Do not trigger a RESET# when the supply voltage is lowered.
Reserved
This pin must be connected to ground (VSS).
Reserved
This pin must be connected to ground (VSS).
• When the Generic host bus interface is selected, this signal is
• When the M6800 host bus interface is selected, this signal is
• When the MC68K host bus interface is selected, this signal is
• When the Generic host bus interface is selected, this pin is
• When the MC68K host bus interface is selected, this pin is
• When the M6800 host bus interface is selected, this pin must
• When the Generic host bus interface is selected, this pin must
• When the MC68K host bus interface is selected, this pin is the
• When the M6800 host bus interface is selected, this pin must
the active-low write strobe (WR#). The bus data is latched on
the rising edge of this signal.
the read/write control signal (R/W#). Data is read from the
S1D13700F01 if this signal is high, and written to the
S1D13700F01 if it is low.
the read/write control signal (RD/WR#). Data is read from the
S1D13700F01 if this signal is high, and written to the
S1D13700F01 if it is low.
WAIT#. During a data transfer, WAIT# is driven active-low to
force the system to insert wait states. It is driven inactive to
indicate the completion of a data transfer. WAIT# is released
to a high impedance state after the data transfer is complete.
For indirect addressing mode, the WAIT# pin can be used to
handshake with the Host.
DTACK#. During a data transfer, DTACK# is driven active-high
to force the system to insert wait states. It is driven inactive to
indicate the completion of a data transfer. DTACK# is released
to a high impedance state after the data transfer is complete.
For indirect addressing mode, the DTACK# pin can be used to
handshake with the Host.
be left unconnected and floating.
be connected to VDD (pulled high).
address strobe (AS#).
be connected to VDD (pulled high).
Description
X42A-A-002-04
S1D13700F01
Page 17