S1D13700F01 Epson Electronics America, Inc., S1D13700F01 Datasheet - Page 48

• Manufacturer Part Number: S1D13700F01
• Description: Embedded Memory Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 48
bit 2
bit 1
bit 0
S1D13700F01
X42A-A-002-04
Parameter
movement
Cursor
SAD1
SAD2
SAD3
SAD4
range
TC/R
C/R
SL1
SL2
L/F
00h to REG[05h] bits 7-0
00h to REG[05h] bits 7-0
REG[00h] bit 5 = 1 (IV)
REG[03h] bits 7-0
REG[04h] bits 7-0
REG[05h] bits 7-0
Continuous movement over whole screen
Single Panel (REG[00h] bit 3 = 0)
Note
Note
The following table summarizes the parameters that must be configured for correct
operation of an LCD panel.
Character Height (M2)
This bit selects the height of the character bitmaps. It is possible to display characters
greater than 16 pixels high by creating a bitmap for each portion of each character and
using graphics mode to reposition them.
When this bit = 0, the character height is 8 pixels.
When this bit = 1, the character height is 16 pixels.
Reserved
The default value for this bit is 0.
Character Generator Select (M0)
This bit determines whether characters are generated by the internal character generator
ROM (CGROM) or character generator RAM (CGRAM). The CGROM contains 160,
5x7 pixel characters which are fixed at fabrication. The CGRAM can contain up to 256
user-defined characters which are mapped at the CG Start Address (REG[1Ah] -
REG[19h]). However, when the CGROM is used, the CGRAM can only contain up to 64,
8x8 pixel characters.
When this bit = 0, the internal CGROM is selected.
When this bit = 1, the internal CGRAM is selected.
Screen Origin Compensation shifts the character font down by one pixel row. If the bot-
tom pixel row of the font is at the bottom of the Screen Block, that row disappears when
REG[00h] bit 5 = 0. To compensate for the bad visual effect, SL can be increased by
one.
If the CGRAM is used (includes CGRAM1 and CGRAM2), only 1 bpp is supported.
Invalid
Second screen block (Start Address = REG[0Eh], REG[0Fh])
00h to REG[05h] bits 7-0
00h to REG[05h] bits 7-0
REG[00h] bit 5 = 0 (IV)
First screen block (Start Address = REG[0Bh], REG[0Ch])
Third screen block (Start Address = REG[11h], REG[12h])
Table 10-2 LCD Parameter Summary
REG[03h] bits 7-0
REG[04h] bits 7-0
REG[05h] bits 7-0
(See Note)
(See Note)
Revision 4.05
Above-and-below configuration: continuous movement over
Fourth screen block (Start Address = REG[13h], REG[14h])
[REG[05h] bits 7-0 + 1] ÷ 2 - 1 [REG[05h] bits 7-0 + 1] ÷ 2 - 1
[REG[05h] bits 7-0 + 1] ÷ 2 - 1 [REG[05h] bits 7-0 + 1] ÷ 2 - 1
REG[00h] bit 5 = 1 (IV)
REG[03h] bits 7-0
REG[04h] bits 7-0
REG[05h] bits 7-0
Dual Panel (REG[00h] bit 3 = 1)
whole screen
Epson Research and Development
Hardware Functional Specification
REG[00h] bit 5 = 0 (IV)
REG[03h] bits 7-0
REG[04h] bits 7-0
REG[05h] bits 7-0
Vancouver Design Center
Issue Date: 2005/12/13