S1D13503 Epson Electronics America, Inc., S1D13503 Datasheet - Page 263
S1D13503
Manufacturer Part Number
S1D13503
Description
S1d13503 Graphics Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D13503.pdf
(270 pages)
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Epson Research and Development
Vancouver Design Center
2.2 SRAM Size and Access Time Requirements
2.2.1 SRAM Size
2.2.2 SRAM Access Time
3 CONCLUSIONS
LCD Panel Options / Memory Requirements
Issue Date: 01/01/30
Memory Size (bytes) =
i.e., 256 colors = 8 bits / pixel, therefore 1 byte (8 bits)
Therefore:
Memory size (bytes) = 76.8 K bytes.
Note
For a detailed description of the memory size requirement, see section 9.4 of the S1D13503 Hardware
Functional Specification, drawing office number X18A-A-001-xx.
To support 256 color modes the S1D13503 must be configured to support a 16-bit data path into display memory (SRAM).
For 16-bit display memory interface the required SRAM access time must be:
Therefore using a 6.0 Mhz input clock:
SRAM access time must be < 127 ns.
Note
For a detail description of the SRAM access time, see section 9.2 of the S1D13503 Hardware Functional
Specification, drawing office number X18A-A-001-xx.
To support a 320x240 256 color panel at 70 Hz refresh, you require a 6.0 MHz input clock, and 76.8K Bytes of 127nsec
access time SRAM.
Memory size (bytes) = (320 * 240) * 8 /8
SRAM Access time < 1/f
-------------------------------------------------------------------------------------------------------------------------------------------- -
Horizontalpixels
OSC
- 40nsec. (3.3v specification)
Verticallines
8
1 pixel
BitsPerPixel
X18A-G-005-05
S1D13503
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