S1D13503 Epson Electronics America, Inc., S1D13503 Datasheet - Page 50

• Manufacturer Part Number: S1D13503
• Description: S1d13503 Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 42
S1D13503
X18A-A-001-08
Symbol
t6a
t6a
t6b
t6b
t6c
t6c
t7a
t7a
t7b
t7b
t10
t10
t11
t1
t1
t2
t2
t3
t3
t4
t5
t8
t8
t9
t9
LP period (single panel mode)
LP period (dual panel mode)
YD hold from LP falling edge (AUX[01] bit 5 = 0)
YD hold from LP falling edge (AUX[01] bit 5 = 1)
LP pulse width (AUX[01] bit 5 = 0)
LP pulse width (AUX[01] bit 5 = 1)
WF delay from LP falling edge
LP setup to XSCL falling edge (AUX[01] bit 5 = 0 and
AUX[03]
bit 2 = 0)
LP hold from XSCL falling edge (AUX[01] bit 5 = 0 and
AUX[03] bit 2 = 0)
LP hold from XSCL falling edge (AUX[01] bit 5 = 0 and
AUX[03] bit 2 = 1)
XSCL falling edge to LP falling edge - single panel mode
(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 0)
XSCL falling edge to LP falling edge - single panel mode
(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 1)
XSCL falling edge to LP falling edge - dual panel mode
(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 0)
XSCL falling edge to LP falling edge - dual panel mode
(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 1)
LP falling edge to XSCL falling edge (AUX[01] bit 5 = 0 and
AUX[03] bit 2 = 0)
LP falling edge to XSCL falling edge (AUX[01] bit 5 = 0 and
AUX[03] bit 2 = 1)
LP falling edge to XSCL falling edge (AUX[01] bit 5 = 1
and AUX[03] bit 2 = 0)
LP falling edge to XSCL falling edge (AUX[01] bit 5 = 1
and AUX[03] bit 2 = 1)
XSCL period (AUX[03] bit 2 = 0)
XSCL period (AUX[03] bit 2 = 1)
XSCL high width (AUX[03] bit 2 = 0)
XSCL high width (AUX[03] bit 2 = 1)
XSCL low width (AUX[03] bit 2 = 0)
XSCL low width (AUX[03] bit 2 = 1)
UD[3:0], LD[3:0] setup to XSCL falling edge (AUX[03] bit 2
= 0)
Table 7-12: LCD Interface Timing - 4-Bit Single and 8-Bit Single/Dual Monochrome Panel
Parameter
HT + HNDP -
2t
13t
8t
13t
12t
2t
6t
5t
2t
2t
7t
6t
4t
2t
2t
t
OSC
t
t
t
OSC
OSC
OSC
OSC
OSC
OSC
4-Bit Single
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
Min
OSC
OSC
n/a
n/a
n/a
n/a
10
0
- 10**
- 10
- 10
- 5
- 5
- 5
- 10
- 10
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
Hardware Functional Specification
Epson Research and Development
Max
20
2(HT + HNDP) -
HT + HNDP -
4t
13t
Vancouver Design Center
8-Bit Single/Dual
8t
15t
13t
31t
29t
4t
2t
6t
5t
2t
4t
2t
4t
2t
9t
7t
8t
4t
4t
2t
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
Min
OSC
OSC
OSC
OSC
10
10
Issue Date: 01/01/29
0
- 10**
- 10
- 10
- 10
- 10
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 5
Max Units
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns