XA-SCC NXP Semiconductors, XA-SCC Datasheet - Page 13
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XA-SCC
Manufacturer Part Number
XA-SCC
Description
Cmos 16-bit Communications Microcontroller
Manufacturer
NXP Semiconductors
Datasheet
1.XA-SCC.pdf
(42 pages)
Philips Semiconductors
1999 Feb 23
SCC3 Write Register 0
SCC3 Write Register 1
SCC3 Write Register 2
SCC3 Write Register 3
SCC3 Write Register 4
SCC3 Write Register 5
SCC3 Write Register 6
SCC3 Write Register 7
SCC3 Write Register 8
SCC3 Write Register 9
SCC3 Write Register 10
SCC3 Write Register 11
SCC3 Write Register 12
SCC3 Write Register 13
SCC3 Write Register 14
SCC3 Write Register 15
SCC3 Write Register 16
SCC3 Write Register 17
SCC3 Read Register 0
SCC3 Read Register 1
Reserved
SCC3 Read Register 3
SCC3 Read Register 6
SCC3 Read Register 7
SCC3 Read Register 8
Reserved
SCC3 Read Register 10
Reserved
DMA Control Register Ch.0 Rx
FIFO Control & Status Reg Ch.0 Rx
Segment Register Ch.0 Rx
Buffer Base Register Ch.0 Rx
Buffer Bound Register Ch.0 Rx
Address Pointer Reg Ch.0 Rx
Byte Count Register Ch.0 Rx
Data FIFO Register Ch.0 Lo Rx
Data FIFO Register Ch.0 Hi Rx
DMA Control Register Ch.1 Rx
FIFO Control & Status Register Ch.1 Rx
Segment Register Ch. 1 Rx
Buffer Base Register Ch. 1 Rx
CMOS 16-bit communications microcontroller
MMR Name
Read/Write or
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
Size
Rx DMA Registers
16
16
16
16
16
SCC3 Registers
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8F6–8FEh
Address
13
Offset
8CAh
8CCh
8CEh
8DAh
8DCh
8DEh
8ECh
8C0h
8C2h
8C4h
8C6h
8C8h
8D0h
8D2h
8D4h
8D6h
8D8h
8E8h
8EAh
8E0h
8E2h
8E4h
8E6h
8EEh
10Ah
10Ch
10Eh
8F0h
8F2h
8F4h
100h
101h
102h
104h
106h
108h
110h
111h
112h
114h
Command register
Tx/Rx Interrupt & data transfer mode
Extended Features Control
Receive Parameter and Control
Tx/Rx misc. parameters & mode
Tx. parameter and control
Sync character or SDLC address field or Match
Character 0
Sync character or SDLC flag or Match Character 1
Transmit Data Buffer
Master Interrupt control
Misc. Tx/Rx control register
Clock Mode Control
Lower Byte of Baud rate time constant
Upper Byte of Baud rate time constant
Misc. Control bits
External/Status interrupt control
Match Character 2 (wr16)
Match Character 3 (wr17)
Tx/Rx buffer and external status
Receive condition status/residue code
Interrupt Pending Register
SDLC byte count low register
SDLC byte count high & FIFO status
Receive Buffer
Loop/clock status
Control Register
Control & Status Register
Points to 64K data segment
Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
Upper Bound (plus 1) on A15–A0
Current Address pointer A15–A0
Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
10Ch = Byte 0 = older,
10Dh = Byte 1 = younger
10Eh = Byte 2 = older,
10Fh = Byte 3 = younger
Control Register
Control & Status Register
Points to 64K data segment
Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
Description
Preliminary specification
XA-SCC
Reset
0000h
0000h
0000h
Value
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
f8h
xx
xx
xx
xx
xx
xx
xx
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