XA-SCC NXP Semiconductors, XA-SCC Datasheet - Page 37
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XA-SCC
Manufacturer Part Number
XA-SCC
Description
Cmos 16-bit Communications Microcontroller
Manufacturer
NXP Semiconductors
Datasheet
1.XA-SCC.pdf
(42 pages)
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Philips Semiconductors
1999 Feb 23
CLKOUT
CASL
(CASH STAYS HIGH)
CMOS 16-bit communications microcontroller
D[7:0]
t
CHAV
ClkOut
D7–D0
RAS
CASL
OE
RAS
A
OE
A
4 Byte Fetch is shown on 8 bit bus, burst can be 2 to 16 bytes.
Data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 9, 12, and 15 in this example).
NOTE 2: If data is held valid on the bus until the earliest of CAS, RAS, or OE rises, then the hold time is met.
1
RAS ADDR
t
CHAV
2
t
CHSL
t
AVSL
t
AVSL
t
CHSL
t
AVSL
t
CHSL
RAS ADDRESS
3
t
Figure 20. DRAM FPM (Fast Page Mode) Burst Code Fetch on 8 Bit Bus
t
CHAH
CHSL
t
CHAH
t
4
CHAV
Figure 19. 16 Bit Read on 8 Bit Bus, DRAM (both FPM and EDO)
t
CAS ADDR
DIS
(EVEN)
5
LS BYTE
6
t
CHSL
t
AVSL
t
DIH
t
CHSH
7
(NOTE 2)
CAS ADDR
t
CPWH
(ODD)
CAS ADDRESS EVEN
8
MS BYTE
37
9
LS BYTE
t
CHAH
t
DIS
10
t
CHAV
CAS ADDR
(EVEN)
11
LS BYTE
t
CHSH
t
DIH
12
t
(NOTE 2)
CPWH
t
DIH
13
CAS ADDR
CAS ADDRESS ODD
(NOTE 2)
(ODD)
t
t
CHSH
CHSH
14
MS BYTE
Preliminary specification
15
t
XA-SCC
DIS
t
MS BYTE
CHAH
SU01141
t
CHAV
t
t
CHSH
OHDE
SU01140
NOTE 2
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