XA-SCC NXP Semiconductors, XA-SCC Datasheet - Page 31

• Manufacturer Part Number: XA-SCC
• Description: Cmos 16-bit Communications Microcontroller
• Manufacturer: NXP Semiconductors

4. To meet hold time, EDO DRAM drives data onto the bus until OE rises, or until a new falling edge of CAS.
5. WARNING: ClkOut is specified at 40pF max. More than 40pf on ClkOut may significantly degrade the ClkOut waveform. Load capacitance
6. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-SCC User Manual for details.
7. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16 bit bus,
8. t
9. The MIN value for this parameter is guaranteed by design and is not tested in production to the specified limit. In those cases where a
Philips Semiconductors
1999 Feb 23
CMOS 16-bit communications microcontroller
for all outputs (except ClkOut) = 80pF.
A3–A1 are incremented for each new word of the burst. On an 8 bit bus, A3–A0 are incremented for each new byte of the burst code fetch.
memory controller to service DRAM. The number of CClks (system clocks) in t
equation in the AC tables. Regardless of what value is programmed into the control register, n will never be less than 2 clocks. Thus at
30MHz system clock, the minimum value for RAS precharge is t
frequency F
maximum value is specified in the table for this parameter, it is tested.
RP
is specified as the minimum high time (thus inactive) on each of the 5 individual CS_RAS[5:1] pins when such pin is programmed in the
C
, is slowed down, t
C
(system clock period) of course becomes greater, and thus t
RP
= ((2 * t
31
C
) –16) = ((2 * 33.33) – 16) = 50.6ns. As the system clock
RP
is programmable, and is represented by n in the t
RP
becomes greater.
Preliminary specification
XA-SCC
RP