XA-SCC NXP Semiconductors, XA-SCC Datasheet - Page 39
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XA-SCC
Manufacturer Part Number
XA-SCC
Description
Cmos 16-bit Communications Microcontroller
Manufacturer
NXP Semiconductors
Datasheet
1.XA-SCC.pdf
(42 pages)
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Philips Semiconductors
1999 Feb 23
CMOS 16-bit communications microcontroller
NOTE: t
It is the minimum high time (thus RAS inactive) between two DRAM bus cycles on the same RAS pin.
CASH, CASL
RAS
CLKOUT
RAS and CAS terminate together. The active low portion of RAS can be programmed to last from 3 to 6 clock cycles.
The high portion of RAS after Refresh can be programmed to last from 2 to 4 clock cycles. See Chapter 3 of XA–SCC User Manual .
RP
XTALIN
RAS
min. is specified for each of the 5 individual RAS pins (CS_RAS[5:1]).
ClkOut
V
t
DD
CHSL
0.45 V
– 0.5
WARNING: ClkOut is specified into 40 pF max, do not overload.
t
CLRL
0.2 V
0.7 V
DD
Figure 25. External Clock Input Drive
DD
– 0.1
Figure 24. RAS Precharge Time
Figure 26. ClkOut Duty Cycle
t
CODH
t
CHCL
Figure 23. REFRESH
t
39
CHSH
t
CLCX
t
RP
t
C
t
CLCH
t
CHCX
SU01146
SU01147
Preliminary specification
SU01144
XA-SCC
SU01145
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