CY39100V Cypress Semiconductor Corporation., CY39100V Datasheet - Page 17

• Manufacturer Part Number: CY39100V
• Description: Cplds At Fpga Densities
• Manufacturer: Cypress Semiconductor Corporation.

Capacitance
DC Characteristics (I/O)
Configuration Parameters
Power-up Sequence Requirements
Notes:
Document #: 38-03039 Rev. *I
10. The number of I/Os which can be used in each I/O bank depends on the type of I/O standards and the number of V
11. See “Power-up Sequence Requirements” below for V
12. 25Ω resistor terminated to termination voltage of 1.5V.
C
C
C
LVCMOS3
LVCMOS2
LVTTL –12 mA
LVTTL –16 mA
LVTTL –24 mA
9.
I/O Standards
• Upon power-up, all the outputs remain three-stated until all
• The part will not start configuration until V
LVTTL –2 mA
LVTTL –4 mA
LVTTL –6 mA
LVTTL –8 mA
I/O
CLK
PCI
LVCMOS18
the V
the part has completed configuration.
V
nominal voltage.
LVCMOS
3.3V PCI
Parameter
SSTL3 II
SSTL2 II
t
HSTL III
HSTL IV
SSTL3 I
SSTL2 I
HSTL II
PCI spec (rev 2.2) requires the IDSEL pin to have capacitance less than or equal to 8 pF. Delta39K Pin Tables starting from page 44, identify all the I/O pins in
a given package, which can be used as IDSEL in a PCI design. All other I/O pins meet the PCI requirement of capacitance less than or equal to 10 pF.
to the application note titled “Delta39K and Quantum38K I/O Standards and Configurations” for details.
RECONFIG
CCJTAG
• The source current limit per I/O bank per V
• The sink current limit per I/O bank per GND pin is 230 mA.
HSTL I
GTL+
Parameter
CC
pins have powered-up to the nominal voltage and
, V
CCCNFG
V
1.25
1.25
0.75
0.75
N/A
1.0
1.5
1.5
0.9
0.9
(V)
REF
, V
Input/Output Capacitance
Clock Signal Capacitance
PCI-compliant
V
CCPLL
CCIO
(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.0
2.5
1.8
3.3
3.3
3.3
2.5
2.5
1.5
1.5
1.5
1.5
[11]
and V
[10]
–15.2 mA V
–0.1 mA
–0.1 mA
–0.1 mA
–1.0 mA
–2.0 mA
–0.5 mA
–7.6 mA V
@ I
–12 mA
–16 mA
–24 mA
–16 mA
–16 mA
Description
–2 mA
–4 mA
–6 mA
–8 mA
–2 mA
–8 mA
–8 mA
–8 mA
–8 mA
OH
CCPRG
[9]
Reconfig pin LOW time before it goes HIGH
=
Capacitance
CCIO
V
OH
V
V
V
V
V
V
V
V
V
have reached
pin is 165 mA.
CCIO
CCIO
CCIO
V
CC
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
(V)
0.9V
CCIO
OH
, V
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.1
2.0
1.7
(min.)
– 0.45V
– 0.62V
– 0.43V 15.2 mA
requirement.
– 0.2V
– 0.2V
CCIO
– 1.1V
– 0.9V
– 0.4V
– 0.4V
– 0.4V
– 0.4V
CCIO
,
Description
V
V
V
36 mA
in
in
in
@ I
0.1 mA
0.1 mA
0.1 mA
1.0 mA
2.0 mA
2.0 mA
1.5 mA
7.6 mA
12 mA
16 mA
24 mA
16 mA
16 mA
24 mA
48 mA
= V
= V
= V
2 mA
4 mA
6 mA
8 mA
8 mA
8 mA
OL
CCIO
CCIO
CCIO
V
[12]
=
OL
• V
• All V
• All V
• Maximum ramp time for all V
Test Conditions
V
and powered up together.
to at least 1.5V before configuration has completed.
voltage in 100 ms.
@ f = 1 MHz 25°C
@ f = 1 MHz 25°C
@ f = 1 MHz 25°C
(V)
0.1V
CC
CC
(max.)
0.45
0.54
0.35
V
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.2
0.2
0.2
0.4
0.7
0.6
0.7
0.5
0.4
0.4
0.4
0.4
, V
CCIO
OL
pins can be powered up in any order. This includes
CCIO
CCIO
CCIO
s (even the unused banks) need to be powered up
s on a bank should be tied to the same potential
V
V
, V
V
V
V
V
V
V
V
0.65V
0.5V
REF
REF
REF
REF
REF
REF
REF
REF
REF
CCJTAG
Min.
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
1.7V
+ 0.18 V
+ 0.18 V
CCIO
+ 0.2
+ 0.2 V
+ 0.2 V
+ 0.1 V
+ 0.1 V
+ 0.1 V
+ 0.1 V
CCIO
V
, V
IH
CCIO
CCCNFG
(V)
V
V
V
V
V
V
V
V
V
V
V
V
Delta39K™ ISR™
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
and GND pins being used. Please refer
Max.
CC
Min.
5
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V
+ 0.3 –0.3V 0.35V
+ 0.5 –0.5V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
+ 0.3 –0.3V V
, V
s should be 0V to nominal
CPLD Family
CCPLL
Min.
200
Min.
Max.
and V
10
12
8
Page 17 of 86
V
IL
V
CCPRG
0.3V
REF
REF
REF
REF
REF
REF
REF
REF
REF
(V)
Max.
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.7V
Unit
Unit
ns
– 0.18
– 0.18
pF
pF
pF
CCIO
– 0.2
– 0.2
– 0.2
– 0.1
– 0.1
– 0.1
– 0.1
CCIO
.
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