CY39100V Cypress Semiconductor Corporation., CY39100V Datasheet - Page 18

• Manufacturer Part Number: CY39100V
• Description: Cplds At Fpga Densities
• Manufacturer: Cypress Semiconductor Corporation.

Switching Characteristics — Parameter Descriptions
Document #: 38-03039 Rev. *I
t
t
t
t
t
t
Synchronous Clocking Parameters
t
t
t
t
t
t
t
t
t
t
t
t
f
f
Product Term Clock
t
t
t
t
Channel Interconnect Parameters
t
t
Miscellaneous Delays
t
t
t
t
Note:
Parameter
13. Add t
PD
EA
ER
PRR
PRO
PRW
MCS
MCH
MCCO
IOS
IOH
IOCO
SCS
SCS2
ICS
OCS
CHZ
CLZ
MAX
MAX2
MCSPT
MCHPT
MCCOPT
SCS2PT
CHSW
CL2CL
CPLD
MCCD
IOD
IOIN
Combinatorial Mode Parameters
CHSW
Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the
horizontal or vertical channel associated with that cluster
Global control to output enable
Global control to output disable
Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical channel
associated with the cluster the macrocell is in
Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel associated
with the cluster that the macrocell is in to any pin output on those same channels
Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a macrocell in the farthest
cluster on the horizontal or vertical channel the pin is associated with
Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a
global clock
Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a
global clock
Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the
cluster that macrocell is in
Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock
Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock
Clock to output of an I/O cell register to the output pin associated with that register
Macrocell clock to macrocell clock through array logic within the same cluster
Macrocell clock to macrocell clock through array logic in different clusters on the same channel
I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with
Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster that the
macrocell is in
Clock to output disable (high-impedance)
Clock to output enable (low-impedance)
Maximum frequency with internal feedback—within the same cluster
Maximum frequency with internal feedback—within different clusters at the opposite ends of a horizontal or vertical
channel
Set-up time for macrocell used as input register, from input to product term clock
Hold time of macrocell used as an input register
Product term clock to output delay from input pin
Register to register delay through array logic in different clusters on the same channel using a product term clock
Adder for a signal to switch from a horizontal to vertical channel and vice-versa
Cluster-to-cluster delay adder (through channels and channel PIM)
Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This parameter
can be added to the t
signal path
Adder for carry chain logic per macrocell
Delay from the input of the output buffer to the I/O pin
Delay from the I/O pin to the input of the channel buffer
to signals making a horizontal to vertical channel switch or vice-versa.
PD
and t
SCS
parameters for each extra pass through the AND/OR array required by a given
Description
Over the Operating Range
Delta39K™ ISR™
[13]
CPLD Family
Page 18 of 86
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