CY39100V Cypress Semiconductor Corporation., CY39100V Datasheet - Page 6

• Manufacturer Part Number: CY39100V
• Description: Cplds At Fpga Densities
• Manufacturer: Cypress Semiconductor Corporation.

Macrocell
Within each logic block there are 16 macrocells. Each
macrocell accepts a sum of up to 16 product terms from the
product term array. The sum of these 16 product terms can be
output in either registered or combinatorial mode. Figure 4
displays the block diagram of the macrocell. The register can
be asynchronously preset or asynchronously reset at the
macrocell level with the separate preset and reset product
terms. Each of these product terms features programmable
polarity. This allows the registers to be preset or reset based
on an AND expression or an OR expression.
An XOR gate in the Delta39K macrocell allows for many
different types of equations to be realized. It can be used as a
polarity mux to implement the true or complement form of an
equation in the product term array or as a toggle to turn the D
flip-flop into a T flip-flop. The carry-chain input mux allows
additional flexibility for the implementation of different types of
logic. The macrocell can utilize the carry chain logic to
implement adders, subtractors, magnitude comparators,
parity tree, or even generic XOR logic. The output of the
macrocell is either registered or combinatorial.
Carry Chain Logic
The Delta39K macrocell features carry chain logic which is
used for fast and efficient implementation of arithmetic opera-
tions. The carry logic connects macrocells in up to four logic
blocks for a total of 64 macrocells. Effective data path opera-
Document #: 38-03039 Rev. *I
FROM PTM
GCLK[3:0]
Up To 16 PTs
PTCLK
CPT0
CPT1
(from macrocell n-1)
Carry In
Clock Mux
C
3
Carry Chain
C
(to macrocell n+1)
Mux
Carry Out
C
Figure 4. Delta39K Macrocell
XOR Input
2
Mux
C
tions are implemented through the use of carry-in arithmetic,
which drives through the circuit quickly. Figure 4 shows that
the carry chain logic within the macrocell consists of two
product terms (CPT0 and CPT1) from the PTA and an input
carry-in for carry logic. The inputs to the carry chain mux are
connected directly to the product terms in the PTA. The output
of the carry chain mux generates the carry-out for the next
macrocell in the logic block as well as the local carry input that
is connected to an input of the XOR input mux. Carry-in and a
configuration bit are inputs to an AND gate. This AND gate
provides a method of segmenting the carry chain in any
macrocell in the logic block.
Macrocell Clocks
Clocking of the register is highly flexible. Four global
synchronous clocks (GCLK[3:0]) and a PTCLK are available
at each macrocell register. Furthermore, a clock polarity mux
within each macrocell allows the register to be clocked on the
rising or the falling edge (see macrocell diagram in Figure 4).
PRESET/RESET Configurations
The macrocell register can be asynchronously preset and
reset using the PRESET and RESET mux. Both signals are
active high and can be controlled by either of two Preset/Reset
product terms (PRC[1:0] in Figure 4) or GND. In situations
where the PRESET and RESET are active at the same time,
RESET takes priority over PRESET.
0
1
0
1
Polarity
Clock
Mux
3
3
C
C
RESET
Mux
C
PRESET
Mux
D
PSET
RES
Q
Q
Delta39K™ ISR™
Output
CPLD Family
Mux
C
To PIM
Page 6 of 86
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