CY39100V Cypress Semiconductor Corporation., CY39100V Datasheet - Page 8

• Manufacturer Part Number: CY39100V
• Description: Cplds At Fpga Densities
• Manufacturer: Cypress Semiconductor Corporation.

The clocks for each port of the Dual-Port configuration are
selected from four global clocks and two local clocks. One
local clock is sourced from the horizontal channel and the
other from the vertical channel. The data outputs of the dual-
port memory can also be registered. Clocks for the output
registers are also selected from four global clocks and two
local clocks. One clock polarity mux per port allows the use of
true or complement polarity for input and output clocking
purposes.
Arbitration
The Dual-Port configuration of the Channel Memory Block
provides arbitration when both ports access the same address
at the same time. Depending on the memory operation being
attempted, one port always gets priority. See Table 2 for
details on which port gets priority for Read and Write opera-
tions. An active-LOW “Address Match” signal is generated
when an address collision occurs.
Table 2. Arbitration Result: Address Match Signal
Becomes Active
FIFO (Channel Memory) Configuration
The channel memory blocks are also configurable as
synchronous FIFO RAM. In the FIFO mode of operation, the
channel memory block supports all normal FIFO operations
without the use of any general-purpose logic resources in the
device.
Document #: 38-03039 Rev. *I
Port A Port B
Read
Write
Read
Write
Read No arbitration
Read Port A gets
Write
Write
required
priority
Port B gets
priority
Port A gets
priority
Arbitration
Result of
Both ports read at the
same time
If Port B requests first then
it will read the current
data. The output will then
change to the newly
written data by Port A
If Port A requests first then
it will read the current
data. The output will then
change to the newly
written data by Port B
Port B is blocked until Port
A is finished writing
Comment
The FIFO block contains all of the necessary FIFO flag logic,
including the Read and Write address pointers. The FIFO flags
include an empty/full flag (EF), half-full flag (HF), and program-
mable almost-empty/full (PAEF) flag output. The FIFO config-
uration has the ability to perform simultaneous Read and Write
operations using two separate clocks. These clocks may be
tied together for a single operation or may run independently
for asynchronous Read/Write (with regard to each other) appli-
cations. The data and control inputs to the FIFO block are
driven from the horizontal or vertical routing channels. The
data and flag outputs are driven onto dedicated routing tracks
in both the horizontal and vertical routing channels. This allows
the FIFO blocks to be expanded by using multiple FIFO blocks
on the same horizontal or vertical routing channel without any
speed penalty.
In FIFO mode, the Write and Read ports are controlled by
separate clock and enable signals. The clocks for each port
are selected from four global clocks and two local clocks.
One local clock is sourced from the horizontal channel and the
other from the vertical channel. The data outputs from the
Read port of the FIFO can also be registered. One clock
polarity mux per port allows using true or complement polarity
for Read and Write operations. The Write operation is
controlled by the clock and the Write enable pin. The Read
operation is controlled by the clock and the Read enable pin.
The enable pins can be sourced from horizontal or vertical
channels.
Channel Memory Initialization
The channel memory powers up in an undefined state, but is
set to a user-defined known state during configuration. To facil-
itate the use of look-up-table (LUT) logic and ROM applica-
tions, the channel memory blocks can be initialized with a
given set of data when the device is configured at power up.
For LUT and ROM applications, the user cannot write to
memory blocks.
Channel Memory Routing Interface
Similar to LBC outputs, the channel memory blocks feature
dedicated tracks in the horizontal and vertical routing channels
for the data outputs and the flag outputs, as shown in
Figure 6. This allows the channel memory blocks to be
expanded easily. These dedicated lines can be routed to I/O
pins as chip outputs or to other logic block clusters to be used
in logic equations.
Delta39K™ ISR™
CPLD Family
Page 8 of 86
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