HY27UG162G5A Hynix Semiconductor, HY27UG162G5A Datasheet

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... NAND FLASH This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash HY27UG162G5A Preliminary HY27UG162G5A Series 1 ...

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... Document Title 2Gbit (128Mx16bit) NAND Flash Memory Revision History Revision No. 0.1 Initial Draft. Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash History Preliminary HY27UG162G5A Series Draft Date Remark Sep. 15. 2006 Preliminary 2 ...

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... Cost effective solutions for mass storage applications NAND INTERFACE - x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - VCC = 2.7 to 3.6V : HY27UG162G5A Memory Cell Array = (1K+32) Bytes x 64 Pages x 2,048 Blocks PAGE SIZE - x16 device : (1K+32 spare) Bytes : HY27UF161G5A BLOCK SIZE ...

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... SUMMARY DESCRIPTION The Hynix HY27UG162G5A series is a 128Mx16bit with spare 4Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently possible to preserve valid data while old data is erased. ...

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... NAND Flash Figure1: Logic Diagram Data Input / Outputs (x16 only) Data Inputs / Outputs Command latch enable Address latch enable Chip Enable Read Enable Write Enable Write Protect Ready / Busy Power Supply Ground No Connection Table 1: Signal Names Preliminary HY27UG162G5A Series 5 ...

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... Figure 2. 63FBGA Contactions, x16 Device (Top view through package) Rev 0.0 / Sep. 2006 Preliminary HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash 6 ...

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... A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Description Table 2: Pin Description Preliminary HY27UG162G5A Series 7 ...

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... D0h - 70h - - 80h 15h - 85h - - 05h E0h - 00h 31h - 34h - - Table 4: Command Set Preliminary HY27UG162G5A Series IO5 IO6 IO7 IO8-IO15 ( (1) L (1) L (1) L (1) A16 A17 A18 (1) L A24 (1) A25 A26 L Acceptable command 4th CYCLE ...

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... Falling X Sequential Read and Data Output During Read (Busy During Program (Busy During Erase (Busy Write Protect X X 0V/Vcc Stand By Table 5: Mode Selection Preliminary HY27UG162G5A Series MODE Command Input Address Input(4 cycles) Command Input Address Input(4 cycles) 9 ...

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... Write Protect pin is not latched by Write Enable to ensure the pro- tection even during the power up. 2.6 Standby. In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced. Rev 0.0 / Sep. 2006 Preliminary HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash 10 ...

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... The command register remains in Read Status command mode until another valid command is written to the command register. Figure 12 details the sequence. Rev 0.0 / Sep. 2006 Preliminary HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash 11 ...

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... The value for A26 from second to the last page address must be same as the value given to A26 in first address. 3. Then the confirm command is issued to start the P/E/R Controller. Rev 0.0 / Sep. 2006 Preliminary HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash 12 ...

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... WP is high. Refer to table 14 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset com- mand is written. Rev 0.0 / Sep. 2006 Preliminary HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash 13 ...

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... Program time for the (last-1)page - (Program command cycle time + Last page data loading time) Rev 0.0 / Sep. 2006 Preliminary HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash 14 ...

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... Random data output is not available in cache read. Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks. Rev 0.0 / Sep. 2006 Preliminary HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash 15 ...

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... The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with the following reference chart (Figure 23). Its value can be determined by the following guidance. Rev 0.0 / Sep. 2006 Preliminary HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash 16 ...

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... Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions. Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Min Typ 2008 VB Table 6: Valid Blocks Number Parameter Table 7: Absolute maximum ratings Preliminary HY27UG162G5A Series Max Unit 2048 Blocks Value Unit 3. ℃ - ℃ ...

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... Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Figure 3: Block Diagram Preliminary HY27UG162G5A Series 18 ...

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... Vcc (max Vcc (max) LO OUT =-400uA =2.1mA =0.4V OL (R/B) Table 9: AC Conditions Preliminary HY27UG162G5A Series 3.3Volt Unit Min Typ Max - 100 ± ± 20 Vccx0 ...

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... Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Symbol Test Condition C V = Symbol t PROG t CBSY Main Array NOP Spare Array NOP t BERS Preliminary HY27UG162G5A Series Min Max Unit - Min Typ Max Unit - 200 700 700 Cycles ...

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... AR t CLR REA t RHZ t CHZ t REH CEA t WHR RST ( Table 12: AC Timing Characteristics Preliminary HY27UG162G5A Series 3.3V olt Unit Min Max 100 ...

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... Internal chip number, cell Type, Number of Simultaneously Programmed Page size, spare size, Block size, Organization Table 14: Device Identifier Coding 1st cycle (Manufacture Code) x16 ADh Table 15: Read ID Data Table Preliminary HY27UG162G5A Series Cache CODING Read Pass: ‘0’ Fail: ‘1’ Don’t care - - - P/E/R Active: ‘ ...

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... Serial Access Time 25ns Reserved 64KB Block Size (Without 128KB Spare Area) 256KB 512KB X8 Organization X16 Table 17: 4th Byte of Device Identifier Description Rev 0.0 / Sep. 2006 HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash IO7 IO6 IO5 IO4 IO7 ...

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... Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Figure 4: Command Latch Cycle Figure 5: Address Latch Cycle Preliminary HY27UG162G5A Series 24 ...

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... This parameter is sampled and not 100% tested. Figure 7: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Figure 6. Input Data Latch Cycle t REH t REA RHZ Dout Dout t RC Preliminary HY27UG162G5A Series t CHZ* t REA RHZ Dout 25 ...

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... I/O x Figure 9: Read1 Operation (Read One Page) Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash t CLR t CLS t CLH CEA t WHR 70h Figure 8: Status Read Cycle Preliminary HY27UG162G5A Series CHZ REA t RH Status Output 26 ...

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... Figure 10: Read1 Operation intercepted by CE Rev 0.0 / Sep. 2006 Preliminary HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash 27 ...

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... Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Figure 11 : Random Data output Preliminary HY27UG162G5A Series 28 ...

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... Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Figure 12: Page Program Operation Preliminary HY27UG162G5A Series 29 ...

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... Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Figure 13 : Random Data In Preliminary HY27UG162G5A Series 30 ...

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... Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Figure 14 : Copy Back Program Preliminary HY27UG162G5A Series 31 ...

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... Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Figure 15 : Cache Program Preliminary HY27UG162G5A Series 32 ...

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... Figure 16: Block Erase Operation (Erase One Block) Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Figure 17: Read ID Operation Preliminary HY27UG162G5A Series 33 ...

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... Figure 18: start address at page start :after 1st latency uninterrupted data flow Rev 0.0 / Sep. 2006 Preliminary HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash 34 ...

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... So possible to connect NAND Flash to a microporcessor. The only function that was removed from standard NAND Flash to make CE don’t care read operation was disabling of the automatic sequential read function. Figure 19: Program Operation with CE don’t-care. Figure 20: Read Operation with CE don’t-care. Rev 0.0 / Sep. 2006 Preliminary HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash 35 ...

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... Figure 22: Power On and Data Protection Timing VTH = 2.5 Volt for 3.3 Volt Supply devices Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Figure 21: Reset Operation Preliminary HY27UG162G5A Series 36 ...

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... Figure 23: Ready/Busy Pin electrical specifications Rev 0.0 / Sep. 2006 Preliminary HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash 37 ...

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... Refer to Table 18 for the recommended procedure to follow if an error occurs during an operation Operation Erase Program Read Figure 24: Bad Block Management Flowchart Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Recommended Procedure Block Replacement Block Replacement or ECC (with 1bit/528byte) ECC (with 1bit/528byte) Table 18: Block Failure Preliminary HY27UG162G5A Series . 38 ...

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... Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 26~29) Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Figure 25: Enable Programming Figure 26: Disable Programming Preliminary HY27UG162G5A Series 39 ...

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... Rev 0.0 / Sep. 2006 2Gbit (128Mx16bit) NAND Flash Figure 27: Enable Erasing Figure 28: Disable Erasing Preliminary HY27UG162G5A Series 40 ...

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... Figure 29. 63-ball FBGA ball array 0.8 mm pitch, Package Outline Symbol FD1 FE FE1 SD SE Table 19: 63-ball FBGA - ball array 0.8mm pitch, Pakage Mechanical Data Rev 0.0 / Sep. 2006 HY27UG162G5A Series 2Gbit (128Mx16bit) NAND Flash Millimeters Min Typ 0.80 0.20 0.60 0.25 0.30 8.90 9.00 4.00 7.20 10.90 11.00 5.60 8.80 0.80 2.50 0.90 2 ...

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... - lank al), P(Lead Free ℃ ℃ ), I(-4 0℃ 5℃ (In clu ck ck lock) : Fixed Ite -fixe d Item Preliminary HY27UG162G5A Series ...