HY27UG162G5A Hynix Semiconductor, HY27UG162G5A Datasheet - Page 12

• Manufacturer Part Number: HY27UG162G5A
• Description: 2gb Nand Flash
• Manufacturer: Hynix Semiconductor

3.3 Block Erase.
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command (60h). Only address A17 to A26 (X16) is valid while A11 to A16 (X16) are ignored. The Erase Confirm
command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of
setup followed by execution command ensures that memory contents are not accidentally erased due to external noise
conditions. At the rising edge of WE after the erase confirm command input, the P/E/R controller handles erase and
erase-verify.
Once the erase process starts, the Read Status Register command may be entered to read the status register.
The system controller can detect the completion of an erase by monitoring the R/B output, or the Status bit (I/O 6) of
the Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When
the erase operation is completed, the Write Status Bit (I/O 0) may be checked.
Figure 16 details the sequence.
3.4 Copy-Back Program.
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an
external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system per-
formance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block
also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a
sequential execution of page-read without serial access and copyingprogram with the address of destination page. A
read operation with "35h" command and the address of the source page moves the whole 2112byte (X8 device) or
1056word (X16 device) data into the internal data buffer.
As soon as the device returns to Ready state, Copy Back command (85h) with the address cycles of destination page
may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Data
input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 15.
"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if
Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external
error detection/correction scheme. For this reason, two bit error correction is recommended for the use
of Copy-Back operation."
Figure 14 shows the command sequence for the copy-back operation.
The Copy Back Program operation requires three steps:
1. The source page must be read using the Read A command (one bus write cycle to setup the command and then
2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is
3. Then the confirm command is issued to start the P/E/R Controller.
Rev 0.0 / Sep. 2006
given with the 4bus cycles to input the target page address. The value for A26 from second to the last page address
4 bus write cycles to input the source page address). This operation copies all 2KBytes from the page into the Page
Buffer.
must be same as the value given to A26 in first address.
2Gbit (128Mx16bit) NAND Flash
HY27UG162G5A Series
Preliminary
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