MT9HTF12872CHY-667 Micron Semiconductor Products, MT9HTF12872CHY-667 Datasheet - Page 4

• Manufacturer Part Number: MT9HTF12872CHY-667
• Description: 512mb, 1gb X72, Ecc, Sr 200-pin Ddr2 Sdram Socdimm
• Manufacturer: Micron Semiconductor Products

Table 6:
PDF: 09005aef828eddb4/Source: 09005aef828edcf5
HTF9C64_128x72CH.fm - Rev. B 10/07 EN
RAS#, CAS#, WE#
(DQS0#–DQS8#)
DQS0–DQS8
DQ0–DQ63
DM0–DM8
CK0, CK0#
BA0–BA2
SA0–SA1
CB0–CB7
Symbol
A0–A13
EVENT#
RESET#
V
ODT0
CKE0
V
SDA
DDSPD
V
S0#
SCL
V
NC
REF
DD
SS
Pin Descriptions
(LVCMOS)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
Output
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
–
Description
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Address inputs: Provide the row address for ACTIVE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one device
bank (A10 LOW, device bank selected by BA0–BA1/BA2) or all device banks (A10
HIGH). The address inputs also provide the op-code during a LOAD MODE command.
Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode
register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE
command. BA0, BA1 (512MB) and BA0–BA2 (1GB).
Clock: CK and CK# are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Output data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM.
Data input mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is
sampled on both edges of DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins. If RDQS is enabled, RDQS0#–RDQS8# are
used only during the READ command.
On-die termination: ODT (registered HIGH) enables termination resistance internal
to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins:
DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD
MODE command.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Presence-detect address inputs: These pins are used to configure the presence-
detect and temperature sensor devices.
Serial clock: SCL is used to synchronize the presence-detect and temperature sensor
data transfer to and from the module.
Check bits.
Data input/output: Bidirectional data bus.
Data strobe: Output with read data, input with write data for source-synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is only
used when differential data strobe mode is enabled via the LOAD MODE command.
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses
and data into and out of the presence-detect portion of the module.
Temperature sensor alarm output: The event pin is used to flag critical module
temperatures.
Power supply: +1.8V ±0.1V.
Serial EEPROM and temperature sensor positive power supply: +3.0V to +3.6V.
SSTL_18 reference voltage (V
Ground.
No connect: These pins are not connected on the module.
512MB, 1GB (x72, ECC, SR) 200-Pin DDR2 SDRAM SOCDIMM
4
DD
/2).
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
©2007 Micron Technology, Inc. All rights reserved.