MT9HTF12872CHY-667 Micron Semiconductor Products, MT9HTF12872CHY-667 Datasheet - Page 8

• Manufacturer Part Number: MT9HTF12872CHY-667
• Description: 512mb, 1gb X72, Ecc, Sr 200-pin Ddr2 Sdram Socdimm
• Manufacturer: Micron Semiconductor Products

I
Table 9:
PDF: 09005aef828eddb4/Source: 09005aef828edcf5
HTF9C64_128x72CH.fm - Rev. B 10/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
t
valid commands; Address bus inputs are switching; Data pattern is same
as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
Active power-down current: All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Operating burst read current: All device banks open; Continuous burst
reads; I
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current:
t
Other control and address bus inputs are switching; Data bus inputs are
switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
DD
RC =
RAS =
CK =
RAS =
RAS =
RAS =
RFC (I
CK =
DD
4W
t
Specifications
t
t
DD
RC (I
CK (I
CK (I
t
t
t
t
OUT
OUT
RAS MIN (I
RAS MAX (I
RAS MAX (I
RAS MAX (I
) interval; CKE is HIGH, S# is HIGH between valid commands;
DD
DD
DD
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
),
); CKE is LOW; Other control and address bus
),
DDR2 I
Values are shown for the MT9HTF6472 DDR2 SDRAM only and are computed from the values specified in the
512Mb (64 Meg x 8) component data sheet
t
t
RAS =
RC =
DD
DD
), AL = 0;
DD
DD
DD
),
t
),
),
),
RC (I
DD
t
t
RAS MIN (I
RCD =
t
t
t
RP =
RP=
RP =
t
CK =
Specifications and Conditions – 512MB
DD
t
t
),
CK =
t
t
RP (I
DD
t
RP (I
RP (I
t
RCD (I
t
CK (I
RRD =
), AL = 0;
DD
DD
t
DD
DD
CK (I
DD
DD
DD
); CKE is HIGH, S# is HIGH between
); CKE is HIGH, S# is HIGH between
DD
); CKE is HIGH, S# is HIGH between
); CKE is HIGH, S# is HIGH between
t
), AL = 0;
), AL =
); REFRESH command at every
RRD (I
); CKE is HIGH, S# is HIGH between
DD
512MB, 1GB (x72, ECC, SR) 200-Pin DDR2 SDRAM SOCDIMM
t
),
CK =
t
DD
RC =
t
RCD (I
),
t
t
CK (I
CK =
t
RCD =
t
t
RC (I
CK =
t
t
DD
CK =
CK =
DD
t
CK (I
) - 1 ×
DD
),
t
t
CK (I
RCD (I
t
),
t
t
OUT
t
CK (I
CK =
CK (I
CK =
DD
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
8
DD
),
CK (I
= 0mA;
DD
DD
DD
t
),
t
CK (I
CK (I
),
); CKE is
); CKE is
DD
);
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
);
);
Symbol
I
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
DD
I
I
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
3Pf
3Ps
2Q
2N
3N
4R
2P
0
1
5
6
7
-80E/
1,035
1,755
1,845
2,070
2,700
-800
900
450
495
360
108
630
63
63
©2007 Micron Technology, Inc. All rights reserved.
1,530
1,620
1,620
2,160
-667
810
945
405
450
315
108
585
63
63
I
DD
Specifications
1,260
1,305
1,530
2,025
-53E
720
855
360
405
270
108
495
63
63
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA