TDA19997HL NXP Semiconductors, TDA19997HL Datasheet - Page 11

• Manufacturer Part Number: TDA19997HL
• Description: Smart Hdmi 1.4 4 1 Switch With Auto-adaptive Equalizer
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[3]
[4]
[5]
TDA19997HL_2
Product data sheet
When 5 V is indicated, a +5 V input signal is available on at least one HDMI input and/or pin AUX_5V is powered.
Bit state dependent.
x = A, B, C, D or E.
8.12.1
8.12 I
8.11 Power supplies
The termination supply voltage must be 3.3 V ± 5 % with a termination resistance of
50 Ω ± 10 % as defined in the HDMI 1.3a specification.
A dedicated 3.3 V ± 10 % supply (powering interrupt pin INT_N/MUTE) is kept for
compatibility with TDA9996. This pin shall be connected to the rest of 3.3 V supply line.
The 1.8 V supply must also be ± 10 %.
A double Power-On Reset (POR) is implemented to manage different delays between
both supply ramp-ups. POR is managed internally without a reset pin. All 1.8 V power
supply pins (V
shorted out).
+5 V from the HDMI connector and AUX_5V pin are used to supply the EDID memory and
the corresponding DDC-bus slave module. To maintain the EDID (volatile memory part)
contents modified by I
AUX_5V pin) constantly available.
The TDA19997HL allows software programming of its internal registers using the I
The I
TDA19997HL’s registers does not influence DDC-bus operation. The TDA19997HL
supports I
I
To access registers, the TDA19997HL uses the I
I
and Standard-mode (100 kHz) are supported by the TDA19997HL. The slave I
address is shown in
The I
non-volatile configuration memory and enable selection of the slave address. The default
slave address value is 1100 000x.
The I
Table 5.
I
address and the subaddress to access the specific register, then it writes the data.
Device type
TDA19997HL
2
2
2
2
C-bus slave device. Pin I2C_SCL is used as the input pin. Both Fast-mode (400 kHz)
C-bus access is explained in
C-bus
C-bus protocol
2
2
2
C-bus is a separate bus to the DDC-bus, ensuring that I
C-bus slave address is 1100 A2 A1 A0 R/W. Address bit values are stored in the
C-bus slave address is identical to TDA9996.
2
C-bus Fast-mode (400 kHz).
Default slave address
DDDC
Bit
, V
A6
Table
1
Rev. 02 — 22 December 2009
DDH
2
C-bus, it is necessary to have +5 V (from HDMI connector or
, V
5.
Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer
DDO
A5
1
Figure
) could be connected together (i.e. these pins must be
3. The I
A4
0
2
C-bus master writes the TDA19997HL
A3
0
2
C-bus. The TDA19997HL acts as an
A2
A2
TDA19997HL
2
C-bus programming of the
A1
A1
© NXP B.V. 2009. All rights reserved.
A0
A0
2
C-bus
2
C-bus.
R/W
11 of 26
1/0