UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 445

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(1) Receive buffer (RXB/RXB2)
(2) Transmit shift register (TXS/TXS2)
(3) Shift register
(4) Reception control parity check
(5) Transmission control parity addition
(6) Selector
This is the register that holds the receive data. Each time one byte of data is received, the receive data is transferred
from the shift register.
If a 7-bit data length is specified, receive data is transferred to bits 0 to 6 of RXB/RXB2, and the MSB of RXB/RXB2
is always “0”.
RXB/RXB2 can be read only by an 8-bit manipulation instruction. The contents of RXB/RXB2 are undefined after RESET
input.
This is the register in which the data to be transmitted is set. Data written to the TXS/TXS2 is transmitted as serial
data.
If a 7-bit data length is specified, bits 0 to 6 of the data written in the TXS/TXS2 are treated as transmit data. A transmit
operation starts when a write to the TXS/TXS2 is performed. The TXS/TXS2 cannot be written to during a transmit
operation.
TXS/TXS2 can be written to only by an 8-bit manipulation instruction. The contents of TXS/TXS2 are undefined after
RESET input.
This is the shift register that converts the serial data input to the RxD pin to parallel data. When one byte of data is
received, the receive data is transferred to the receive buffer.
The shift register cannot be manipulated directly by the CPU.
Receive operations are controlled in accordance with the contents set in the asynchronous serial interface mode register
(ASIM/ASIM2). In addition, parity error and other error checks are performed during receive operations, and if an error
is detected, a value is set in the asynchronous serial interface status register (ASIS/ASIS2) according to the type of
error.
Transmission operation is controlled by appending a start bit, parity bit, and stop bit to the data written to the transmit
shift registers (TXS and TXS2) in accordance with the contents set to the asynchronous serial interface mode registers
(ASIM and ASIM2).
Selects the baud rate clock source.
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
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