UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 459
UPD784026
Manufacturer Part Number
UPD784026
Description
16/8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD784026.pdf
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16.3.3 Basic Operation Timing
by bit in MSB-first or LSB-first order in synchronization with the serial clock.
the next data transmit or receive operation is started.
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit
MSB/LSB switching is specified by the DIR1 bit of the clock serial interface mode register (CSIM1).
Transmit data is output in synchronization with the fall of SCK1, and receive data is sampled on the rise of SCK1.
An interrupt request (INTCSI1) is generated on the 8th rise of SCK1.
When the internal clock is used as SCK1, SCK1 output is stopped on the 8th rise of SCK1 and SCK1 remains high until
3-wire serial I/O mode timing is shown in Figure 16-12.
(a) MSB-first
SO1 (Output)
SI1 (Input)
INTCSI1
SCK1*
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
Figure 16-12 3-Wire Serial I/O Mode Timing (1/2)
1
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
DI7
2
Start of transfer synchronized with fall of SCK1
Execution of instruction that writes to SIO1, etc.
DI6
3
DI5
4
DI4
5
DI3
6
DI2
7
DI1
8
DI0
Transfer End
Interrupt Generation
* Master CPU: Output
Slave CPU : Input
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