FIDO1100PQF208IR1 Innovasic Semiconductor Inc., FIDO1100PQF208IR1 Datasheet - Page 11

• Manufacturer Part Number: FIDO1100PQF208IR1
• Description: 32-bit Real-time Communications Controller
• Manufacturer: Innovasic Semiconductor Inc.

Flexible Input Deterministic Output (fido ® )
32-Bit Real-Time Communications Controller
Table 2. Test Pin Descriptions
The JTAG Interface is used for controlling the SPIDER Debug Features of the fido1100.
2.3
TDO
TMS
TCK
TDI
Pin
Breakpoints—Eight hardware context-aware breakpoints that can be chained to set up
if/then triggering conditions.
– Hardware breakpoints are enabled in software or over JTAG
Watchpoints—Eight hardware watchpoints.
Trace—Follow program execution with trace buffers.
– Single address, single buffer, and circular buffer trace modes
– Trace buffer can be written anywhere in the address space or to a peripheral
Debug Control—Hardware single-step and context status control.
– Access to all memory and registers that are accessible to software
– Byte, word, and long-word access in full-address mode or offset mode
– Invalid address access (keystroke errors) over JTAG will not kill the session
– Direct programming of FLASH on the evaluation board without target software
– Built-in hardware support to halt contexts and execute single instructions without
– JTAG access to registers, stack space, etc., even if the processor is halted
Statistical Profiling—SPIDER provides statistical software profiling to identify critical
pieces of code.
Internal Memory and Memory Management
User SRAM—Internal 24-Kbyte memory that can be used by applications for general
purpose data needs or as trace buffers.
Relocatable Rapid Execution Memory (RREM)—Internal 32-Kbyte memory that can be
used as an instruction source for code that requires maximum execution speed.
Direction
In
In
In
In
support
software
Test Data Output—The tri-state test data output changing on the falling edge of the
TCK input. This is actively driven only in the shift-DR and shift-IR controller states.
Test Data Input—The test data input sampled on the rising edge of the TCK input.
Test Mode Select Input—The test mode select input used to sequence the TAP
controller state machine. If TMS is a 1 for 5 clock cycles, it sends the TAP controller
into reset. If TMS is 0, the TAP controller goes to IDLE.
Test Clock Input—All JTAG commands and serial data are synchronized by this
signal.
®
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Description
November 20, 2009
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