FIDO1100PQF208IR1 Innovasic Semiconductor Inc., FIDO1100PQF208IR1 Datasheet - Page 61

• Manufacturer Part Number: FIDO1100PQF208IR1
• Description: 32-bit Real-time Communications Controller
• Manufacturer: Innovasic Semiconductor Inc.

Flexible Input Deterministic Output (fido ® )
32-Bit Real-Time Communications Controller
The TxWAIT setting determines when first to start sampling the low active RDY_N line
(labeled with an arrow marked ―1‖ in the diagram).
In the case of a write transfer after the low active RDY_N line is first sampled low
(labeled with an arrow marked ―2‖ in the diagram), the write cycle will complete on the
next rising edge of the clock as shown (labeled with an arrow marked ―3‖ in the
diagram).
In the case of a read transfer once the low active RDY_N line is first sampled low
(labeled with an arrow marked ―2‖ in the diagram), the read data will be sampled on the
second rising edge of the clock.
The write-cycle timing is controlled by TwWAIT setting (shown as TxWAIT in the
diagram), 1–16 clocks.
The read-cycle timing is controlled by TrWAIT setting (shown as TxWAIT in the
diagram), 1–16 clocks.
If the RDY_N line never goes low, the cycle will end (as a bus error) after a timeout of
TxWAIT + 256 clocks.
If the RDY_N line is unused (tied low via an internal pull down) or goes low
immediately, the cycle will be controlled by TxWAIT as described above.
In the case of a write transfer, the write-enable signal (WE_N) goes active (low) 0–3
clocks after the CS_N goes low.
Figure 21. External Bus Timing for a 32-Bit Transfer (with RDY_N)
®
UNCONTROLLED WHEN PRINTED OR COPIED
Page 61 of 81
IA211080807-06
November 20, 2009
http://www.Innovasic.com
Customer Support:
Data Sheet
1-888-824-4184