FIDO1100PQF208IR1 Innovasic Semiconductor Inc., FIDO1100PQF208IR1 Datasheet - Page 68

• Manufacturer Part Number: FIDO1100PQF208IR1
• Description: 32-bit Real-time Communications Controller
• Manufacturer: Innovasic Semiconductor Inc.

Flexible Input Deterministic Output (fido ® )
32-Bit Real-Time Communications Controller
longer burst that is being truncated. The new READ command should be issued x cycles before
the clock edge at which the last desired data element is valid, where x equals the CAS latency
minus one (see Figure 28). For CAS latencies of two and three, data element n + 3 is either the
last of a burst of four or the last desired of a longer burst. The 64 Mbyte SDRAM uses a
pipelined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A READ command can be initiated on any clock cycle following a previous READ
command. Full-speed random read accesses can be performed to the same bank, as shown in
Figure 16 or each subsequent READ may be performed to a different bank.
9.2.5 SDRAM Write Operation, Write Burst, Write-to-Write, and Write-to-Precharge
WRITE bursts are initiated with a WRITE command.
The starting column and bank addresses are provided with the WRITE command, and auto
precharge is either enabled or disabled for that access. If auto precharge is enabled, the row
Timing
®
Figure 28. SDRAM Read Burst Timing
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IA211080807-06
November 20, 2009
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