FIDO1100PQF208IR1 Innovasic Semiconductor Inc., FIDO1100PQF208IR1 Datasheet - Page 60

• Manufacturer Part Number: FIDO1100PQF208IR1
• Description: 32-bit Real-time Communications Controller
• Manufacturer: Innovasic Semiconductor Inc.

Flexible Input Deterministic Output (fido ® )
32-Bit Real-Time Communications Controller
9.1.2 External Bus Timing for a 32-Bit Transfer (with RDY_N)
This timing is programmable via the External Bus Chip Select Timing Register (see Figure 21).
The write-cycle timing is controlled by TwWAIT setting (shown as TxWAIT in the
diagram), 1–16 clocks.
The read-cycle timing is controlled by TrWAIT setting (shown as TxWAIT in the
diagram), 1–16 clocks.
The output-enable signal (OE_N) goes active (low) 0–3 clocks (TOE) after the chip
select.
The output-enable signal (OE_N) goes inactive (hi) coincident with the chip select.
The write-enable signal (WE_N) goes active (low) 0–3 clocks (TWEF) after the chip
select (first cycle only). For subsequent cycles, the WE_N line will go active (low) 0–3
clocks (TWEF) after the address bus changes.
The write-enable signal (WE_N) goes inactive (hi) 0–3 clocks (TWER) before the end of
the wait time and hence before the address bus changes (subsequent cycles). This is
when the data is considered ―written.‖
Figure 20. External Bus Timing for a Single, 32-Bit Cycle (without RDY_N)
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IA211080807-06
November 20, 2009
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