ST92195C STMicroelectronics, ST92195C Datasheet
ST92195C
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ST92195C Summary of contents
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... Real-Time Operating System available from third parties Pin-compatible EPROM and OTP devices available Device Summary Device ROM ST92195C3 ST92195C4 48K ST92195C5 ST92195C6 56K ST92195C7 64K ST92195C8 84K ST92195C9 96K ST92195D5 48K ST92195D6 56K ST92195D7 64K ST92195C/D PSDIP56 TQFP64 tools, including ...
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... ST92195C GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.1 ST9+ Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.3 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.4 TV Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.5 On Screen Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.6 Teletext and Display Storage RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.7 Teletext, VPS and WSS Data Slicers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.8 Voltage Synthesis Tuning Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.9 PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.10 Serial Peripheral Interface (SPI 1.1.11 Standard Timer (STIM 1.1.12 I²C Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 ...
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DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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I/O STATUS AFTER WFI, HALT AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Hamming Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST92E195C/D-ST92T195C 217 1 GENERAL DESCRIPTION . . . . . . . . . . ...
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... ST92195C/D - 7/249 ...
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... The intelligent on-chip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical application tasks to get the maximum use of core resources. The ST92195C/D MCU support low power consump- tion and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 ST9+ Core ...
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... A second line is used for a syn- chronous clock signal. ST92195C/D - GENERAL DESCRIPTION 1.1.11 Standard Timer (STIM) The ST92195C and ST92195D have one or two Standard Timer(s) that include a programmable 16-bit down counter and an associated 8-bit pres- caler with Single and Continuous counting modes. ...
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... SYNTHESIS STANDARD STOUT0 1) TIMER SDA1/SCL1 2) I²C SDA2/SCL2 All alternate functions (Italic characters) are mapped on Ports and 5 Note 1: One standard timer on ST92195C devices, two standard timers on ST92195D devices Note 2: I²C available on ST92195D devices only 10/249 I/O 8 P0[7:0] PORT 0 I/O P2[5:0] 6 PORT 2 ...
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... PIN DESCRIPTION Figure 2. 64-Pin Package Pin-Out 64 GND 1 AIN4/P0.2 P0.1 P0.0 CSO/RESET0/P3.7 P3.6 P3.5 P3 SDA1/SDO/SDI/P5.1 SCL1/INT2/SCK/P5 JTDO 16 16 N.C. = Not connected ST92195C/D - GENERAL DESCRIPTION P4.7/PWM7/EXTRG/STOUT0 P4.6/PWM6 P4.5/PWM5/SDA2 P4.4/PWM4/SCL2 P4.3/PWM3/TSLU/HT P4.2/PWM2 P4.1/PWM1 P4.0/PWM0 VSYNC HSYNC/CSYNC AVDD1 PXFM JTRST0 GND N.C. 32 11/249 ...
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... ST92195C/D - GENERAL DESCRIPTION PIN DESCRIPTION (Cont’d) Figure 3. 56-Pin Package Pin-Out CSO/RESET0/P3.7 SDA1/SDI/SDO/P5.1 SCL1/SCK/INT2/P5.0 V RESET Reset (input, active low). The ST9+ is ini- tialised by the Reset signal. With the deactivation of RESET, program execution begins from the Program memory location pointed to by the vector contained in program memory locations 00h and 01h ...
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... PIN DESCRIPTION (Cont’d) Figure 4. ST92195C/D Required External Components (56-pin package) ST92195C/D - GENERAL DESCRIPTION 13/249 ...
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... ST92195C/D - GENERAL DESCRIPTION PIN DESCRIPTION (Cont’d) Figure 5. ST92195C/D Required External Components (64-pin package ...
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... P4.2 42 P4.3 43 ST92195C/D - GENERAL DESCRIPTION Important : Note that open-drain outputs are for logic levels only and are not true open drain. 1.2.1 I/O Port Alternate Functions. Each pin of the I/O ports of the ST92195C/D may assume software programmable Alternate Func- tions (see Table 1). Alternate Functions 10 I/O 9 I/O 8 ...
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... ST92195C/D - GENERAL DESCRIPTION Port Pin No. General Purpose I/O TQFP64 SDIP56 Name P4.4 44 P4.5 45 P4.6 46 All ports useable for general pur- P4.7 pose I/O (input, 47 output or bidi- rectional) P5.0 14 P5.1 13 Note 1: I²C available on ST92195D devices only. Table 2. I/O Port Styles Pins Weak Pull-Up P0[7:0] no P2[5,4,3,2] no P2[1,0] no P3.7 yes P3[6,5,4] no P4[7:0] no P5[1:0] no Legend: AF= Alternate Function, BID = Bidirectional Open Drain ...
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... Example 2: PWM 0 output AF: PWM0, Port: P4.0 Write the port configuration bits (for output push- pull): P4C2.0=0 P4C1.0=1 P4C0.0=1 ST92195C/D - GENERAL DESCRIPTION Example 3: ADC analog input AF: AIN1, Port : P2.1, Port style: does not apply to analog inputs Write the port configuration bits: P2C2.1=1 P2C1.1=1 P2C0.1=1 ...
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... ST92195C3/C4/C5 48K 00 0000h ST92195D5 ST92195C6 56K 00 0000h ST92195D6 ST92195C7 64K 00 0000h ST92195D7 ST92195C8 84K 00 0000h ST92195C9 96K 00 0000h Figure 6. ST92195C/D Memory Map 229FFFh max. 8 Kbytes TDSRAM 228000h 20FFFFh Internal Internal RAM RAM 1) 256 bytes 1) 20FF00h 512 bytes 20FE00h 017FFFh 1) 96 Kbytes ...
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... REGISTER MAP The following pages contain a list of ST92195C/D registers, grouped by peripheral or function. Be very careful to correctly program both: – The set of registers dedicated to a particular function or peripheral. – Registers common to other functions. Table 3. Group F Pages Register Map Register R255 Res. ...
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... ST92195C/D - GENERAL DESCRIPTION Table 4. Detailed Register Map Group F Reg. Register Page Block No. Name Dec. R224 P0DR I/O R226 P2DR Port R227 P3DR 0:5 R228 P4DR R229 P5DR R230 CICR R231 FLAGR N/A R232 R233 R234 PPR Core R235 MODER R236 USPHR R237 USPLR R238 ...
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... DPR3 21 R244 CSR R248 ISR R249 DMASR Ext.Mem. R246 EMR2 ST92195C/D - GENERAL DESCRIPTION Description Port 4 Configuration Register 0 Port 4 Configuration Register 1 Port 4 Configuration Register 2 Port 5 Configuration Register 0 Port 5 Configuration Register 1 Port 5 Configuration Register 2 VPS Status Register VPS Data Register 0 VPS Data Register 1 ...
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... ST92195C/D - GENERAL DESCRIPTION Group F Reg. Register Page Block No. Name Dec. R240 HBLANKR R241 HPOSR R242 VPOSR R243 FSCCR R244 HSCR R245 NCSR R246 CHPOSR R247 CVPOSR 32 R248 SCLR R249 SCHR OSD R250 DCM0R R251 DCM1R R252 TDPR R253 DE0R R254 DE1R ...
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... I²CDR R244 I²CSTR2 R245 I²CSTR1 R251 PCONF 55 RCCU R254 SDRATH ST92195C/D - GENERAL DESCRIPTION Description .. .. 40-byte buffer .. TDSRAM Buffer Control Register Multi-byte Transfer Start Address Register 1 Multi-byte Transfer Start Address Register 0 TDSRAM Interface Configuration Register PLL Clock Control Register Slicer Clock Control Register ...
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... ST92195C/D - GENERAL DESCRIPTION Group F Reg. Register Page Block No. Name Dec. R240 CM0 R241 CM1 R242 CM2 R243 CM3 R244 CM4 R245 CM5 PWM R246 CM6 59 R247 CM7 R248 ACR R249 CCR R250 PCTL R251 OCPL R252 OER R254 VSDR1 VS R255 VSDR2 ...
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... Group F, Figure 7. Single Program and Data Memory Address Space Mbytes ST92195C/D - DEVICE ARCHITECTURE which hold data and control bits for the on-chip peripherals and I/Os. – A single linear memory space accommodating both program and data ...
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... ST92195C/D - DEVICE ARCHITECTURE MEMORY SPACES (Cont’d) Figure 8. Register Groups 255 F PAGED REGISTERS 240 239 E SYSTEM REGISTERS 224 223 Figure 10. Addressing the Register File REGISTER FILE 255 F PAGED REGISTERS 240 239 E SYSTEM REGISTERS ...
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... System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. ST92195C/D - DEVICE ARCHITECTURE Therefore if the Page Pointer, R234, is set to 5, the instructions: spp #5 ld R242, r4 will load the contents of working register r4 into the third register of page 5 (R242) ...
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... ST92195C/D - DEVICE ARCHITECTURE 2.3 SYSTEM REGISTERS The System registers are listed in Registers (Group E). They are used to perform all the important system settings. Their purpose is de- scribed in the following pages. Refer to the chapter dealing with I/O for a description of the PORT[5:0] Data registers. Table 6. System Registers (Group E) ...
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... Logical (and, andw, or, xorw, cpl), Increment and Decrement (inc, incw, dec, ST92195C/D - DEVICE ARCHITECTURE decw), Test (tm, tmw, tcm, tcmw, btset). In most cases, the Zero flag is set when the contents of the register being used as an accumulator be- come zero, following one of the above operations. ...
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... ST92195C/D - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include a Sdm instruction. Note that code is always pointed to by the Code Pointer (CSR) ...
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... The bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: Single register pointing mode 1: Twin register pointing mode Bits 1:0: Reserved. Forced by hardware to zero. ST92195C/D - DEVICE ARCHITECTURE POINTER 1 REGISTER (RP1) R233 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) 0 ...
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... ST92195C/D - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) Figure 11. Pointing to a single group of 16 registers REGISTER BLOCK GROUP NUMBER REGISTER FILE r15 3 1 GROUP 32/249 Figure 12. Pointing to two groups of 8 registers ...
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... Mode Register The Mode Register allows control of the following operating parameters: – Selection of internal or external System and User Stack areas, ST92195C/D - DEVICE ARCHITECTURE – Management of the clock frequency, – Enabling of Bus request and Wait signals when interfacing to external memory. MODE REGISTER (MODER) ...
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... ST92195C/D - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) state by setting the HIMP bit. When this bit is reset, it has no effect. Setting the HIMP bit is recommended for noise re- duction when only internal Memory is used. If Port 1 and/or 2 are declared as an address AND as an I/O port (for example: P10... P14 = Address, and P15 ...
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... STACK POINTER (LOW) points to STACK ST92195C/D - DEVICE ARCHITECTURE SYSTEM STACK POINTER HIGH REGISTER (SSPHR) R238 - Read/Write Register Group: E (System) Reset value: undefined 0 7 USP8 SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SYSTEM STACK POINTER LOW REGISTER (SSPLR) ...
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... ST92195C/D - DEVICE ARCHITECTURE 2.4 MEMORY ORGANIZATION Code and data are accessed within the same line- ar address space. All of the physically separate memory areas, including the internal ROM, inter- nal RAM and external memory are mapped in a common address space. The ST9 provides a total addressable memory space of 4 Mbytes. This address space is ar- ranged as 64 segments of 64 Kbytes ...
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... F1h R241 DPR0 F0h R240 ST92195C/D - DEVICE ARCHITECTURE sub-divided into 2 main groups: a first group of four 8-bit registers (DPR[3:0]), and a second group of three 6-bit registers (CSR, ISR, and DMASR). The first group is used to extend the address during Data Memory access (DPR[3:0]). The second is ...
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... ST92195C/D - DEVICE ARCHITECTURE 2.6 ADDRESS SPACE EXTENSION To manage 4 Mbytes of addressing space necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address into a 22-bit physical address. There are 2 different ways to do this de- pending on the memory involved and on the oper- ation being performed ...
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... DMA Fetching interrupt 3 instruction or DMA access to Program Memory ST92195C/D - DEVICE ARCHITECTURE Most of these registers do not have a default value after reset. 2.7.1 DPR[3:0]: Data Page Registers The DPR[3:0] registers allow access to the entire 4 Mbyte memory space composed of 256 pages of 16 Kbytes. 2.7.1.1 Data Page Register Relocation ...
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... ST92195C/D - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set. 7 DPR0_7 DPR0_6 DPR0_5 DPR0_4 DPR0_3 DPR0_2 DPR0_1 DPR0_0 Bits 7:0 = DPR0_[7:0]: These bits define the 16- Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to ex- tend the address during a Data Memory access ...
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... Reset value: undefined ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0 ST92195C/D - DEVICE ARCHITECTURE ISR and ENCSR bit (EMR2 register) are also de- scribed in the chapter relating to Interrupts, please refer to this description for further details. Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = ISR_[5:0]: These bits define the 64- ...
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... ST92195C/D - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) Figure 18. Memory Addressing Scheme (example) DPR3 DPR2 DPR1 DPR0 DMASR ISR CSR 42/249 4M bytes 3FFFFFh 16K 294000h 240000h 23FFFFh 20C000h 16K 200000h 16K 1FFFFFh 040000h 03FFFFh 64K 030000h 020000h 64K 010000h 16K 00C000h 64K ...
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... If this bit is reset (default condition), the CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, the ISR is ST92195C/D - DEVICE ARCHITECTURE used instead of the CSR, and the interrupt stack frame is kept exactly as in the original ST9 (only the PC and flags are pushed). This avoids the ...
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... ST92195C/D - INTERRUPTS 3 INTERRUPTS 3.1 INTRODUCTION The ST9 responds to peripheral and external events through its interrupt channels. Current pro- gram execution can be suspended to allow the ST9 to execute a specific response routine when such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism ...
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... No more than 8 routines can be nested inter- ST9+ rupt routine at level N is being serviced, no other PC, FLAGR, Interrupts located at level N can interrupt it. This CSR guarantees a maximum number of 8 nested levels No limit including the Top Level Interrupt request. Across segments ST92195C/D - INTERRUPTS 45/249 ...
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... If two or more requests occur at the same time and at the same priority level, an on-chip daisy chain, specific to every ST9 version, selects the channel with the highest position in the chain, as shown in Table 7. on page 46 Table 7. Daisy Chain Priority for the ST92195C/D Highest Position INTA0 INT0/WDT INTA1 ...
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... INT 2 INT 3 CPL = 7 INT 4 CPL = 7 MAIN CPL = 7 ST92195C/D - INTERRUPTS Figure 21 on INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5 47/249 ...
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... ST92195C/D - INTERRUPTS ARBITRATION MODES (Cont’d) Example 2 In the second example, (more complex, on page 48), each interrupt service routine sets In- terrupt Enable with the ei instruction at the begin- ning of the routine. Placed here, it minimizes re- sponse time for requests with a higher priority than the one being serviced. ...
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... INT 2 INT6 CPL=2 INT 3 INT2 CPL=3 INT 4 CPL=4 CPL2 < CPL4: Serviced next ST92195C/D - INTERRUPTS INTERRUPT 0 HAS PRIORITY LEVEL 0 INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5 INTERRUPT 6 HAS PRIORITY LEVEL 6 INT 6 CPL=6 MAIN ...
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... ST92195C/D - INTERRUPTS ARBITRATION MODES (Cont’d) End of Interrupt Routine The iret Interrupt Return instruction executes the following steps: – The Flag register is popped from system stack. – If ENCSR is set, CSR is popped from system stack. – The PC high byte is popped from system stack. ...
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... Channel INT.A1: 011=3 INTA0 INT.B0: 100=4 INTA1 INT.B1: 101=5 INTB0 VR000151 INTB1 A/D Converter / I²C INTC0 INTC1 INTD0 INTD1 ST92195C/D - INTERRUPTS shows an example of priority gives an overview of the Ex- Internal Interrupt External Interrupt Source Source Timer/Watchdog INT0 Standard Timer 0 None SPI Interrupt INT2 None ...
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... ST92195C/D - INTERRUPTS 52/249 ...
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... Mask bit IMC1 INTS1 TED0 “0” VECTOR Priority level “1” Mask bit IMD0 TED1 VECTOR Priority level Mask bit IMD1 ST92195C/D - INTERRUPTS PL2A PL1A 0 INT A0 request Pending bit IPA0 IMA0 PL2A PL1A ...
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... ST92195C/D - INTERRUPTS 3.7 TOP LEVEL INTERRUPT The Top Level Interrupt channel can be assigned either to the external pin NMI or to the Timer/ Watchdog according to the status of the control bit EIVR.TLIS (R246.2, Page 0). If this bit is high (the reset condition) the source is the external pin NMI. ...
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... ST92195C/D - INTERRUPTS cycles (DIVWS and MUL instructions for other instructions. For a non-maskable Top Level interrupt, the re- ...
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... ST92195C/D - INTERRUPTS 3.10 INTERRUPT REGISTERS CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: System Reset value: 1000 0111 (87h) 7 GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0 Bit 7 = GCEN: Global Counter Enable. This bit enables the 16-bit Multifunction Timer pe- ripheral. 0: MFT disabled 1: MFT enabled Bit 6 = TLIP: Top Level Interrupt Pending ...
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... Bit 7 = IMD1: INTD1 Interrupt Mask Bit 6 = IMD0: INTD0 Interrupt Mask Bit 5 = IMC1: INTC1 Interrupt Mask Bit 4 = IMC0: INTC0 Interrupt Mask ST92195C/D - INTERRUPTS Bit 3 = IMB1: INTB1 Interrupt Mask Bit 2 = IMB0: INTB0 Interrupt Mask Bit 1 = IMA1: INTA1 Interrupt Mask Bit 0 = IMA0: INTA0 Interrupt Mask These bits are set and cleared by software ...
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... ST92195C/D - INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 - Read/Write Register Page: 0 Reset value: xxxx 0110b (x6h TLTEV TLIS IAOS EWEN Bits 7:4 = V[7:4]: Most significant nibble of Exter- nal Interrupt Vector . These bits are not initialized by reset. For a repre- ...
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... CSR on the stack. Full compatibility with the original ST9 is lost in this case, because the interrupt stack frame is different; this difference, however, should not affect the vast majority of programs. ST92195C/D - INTERRUPTS 59/249 ...
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... ST92195C/D - RESET AND CLOCK CONTROL UNIT (RCCU) 4 RESET AND CLOCK CONTROL UNIT (RCCU) 4.1 INTRODUCTION The Reset Control Unit comprises two distinct sec- tions: – An oscillator that uses an external quartz crystal. – The Reset/Stop Manager, which detects and flags Hardware, Software and Watchdog gener- ated resets ...
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... Figure 31. External Clock n EXTERNAL CLOCK OSCIN OSCOUT NC CLOCK INPUT ST92195C/D - RESET AND CLOCK CONTROL UNIT (RCCU) The following table is relative to the fundamental quartz crystal only; assuming: Max – Rs: parasitic series resistance of the quartz crys- 2.4 tal (upper limit) – C0: parasitic capacitance of the crystal (upper ...
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... ST92195C/D - RESET AND CLOCK CONTROL UNIT (RCCU) 4.4 CLOCK CONTROL REGISTERS MODE REGISTER (MODER) R235 - Read/Write Register Group: E (System) Reset Value: 1110 0000 (E0h DIV2 PRS2 PRS1 Bits 7:6 = Bits described in Device Architecture chapter. Bit 5 = DIV2: OSCIN Divided This bit controls the divide by 2 circuit which oper- ates on the OSCIN Clock ...
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... RCCU PLL and CSDU are turned off when a HALT instruction is performed. 1: RCCU will reset the microcontroller when a HALT instruction is performed. Bits 6:0= Reserved bits. Leave in their reset state. ST92195C/D - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK SLOW DOWN UNIT RATIO REGISTER (SDRATH) R254 - Read/Write Register Page: 55 ...
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... ST92195C/D - TIMING AND CLOCK CONTROLLER 5 TIMING AND CLOCK CONTROLLER 5.1 FREQUENCY MULTIPLIERS Three on-chip frequency multipliers generate the proper frequencies for: the Core/Real time Periph- erals, the Display related time base and the Slicer over-sampling clock for the Teletext Data slicer. Figure 32. Timing and Clock Controller Block Diagram ...
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... MCFM Main Clock PLL Filter Input Pin PXFM Pixel Clock PLL Filter Input Pin TXCF Teletext PLL Clock Filter input Pin ST92195C/D - TIMING AND CLOCK CONTROLLER 4 MHz 4 MHz 4 MHz Note: 24 MHz is the max. CPU authorized frequency. Table 13. DOTCK/2 frequency choices SKW ...
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... ST92195C/D - TIMING AND CLOCK CONTROLLER Figure 33. Programming the MCCR Set the PLL frequency FML (3:0) Start the PLL by setting FMEN = 1 Wait for Clock Stabilization Validate PLL as Main CPU Clock Figure 34. Programming the SKCCR, PXCCR Set the PLL frequency SKW (3:0) Start the PLL by setting ...
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... Frequency Multiplier which generates the internal multiplied frequency Fimf. The Fimf value is calculated as follows : Fimf = Crystal frequency * [ (FML(3: ST92195C/D - TIMING AND CLOCK CONTROLLER SKEW CLOCK CONTROL REGISTER (SKCCR) R254 - Read/ Write Register Page: 39 Reset value: 0000 0000 (00h) ...
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... ST92195C/D - TIMING AND CLOCK CONTROLLER REGISTER DESCRIPTION (Cont’d) PLL CLOCK CONTROL REGISTER (PXCCR) R251 - Read/Write Register Page: 39 Reset value: 0000 0000 (00h PXCE Bit 7= PXCE. Pixel Clock Enable bit. 0: Pixel and TDSRAM interface clocks are blocked 1: Pixel clock is sent to the display controller and TDSRAM interface ...
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... P1C2 P5C2 F5h P1C1 P5C1 F4h P1C0 P5C0 F3h Reserved Reserved F2h P0C2 P4C2 F1h P0C1 P4C1 F0h P0C0 P4C0 ST92195C/D - I/O PORTS Fig- GROUP F PAGE 43 P9DR R255 P9C2 R254 P9C1 R253 P9C0 R252 P8DR R251 P8C2 R250 P8C1 R249 P8C0 R248 ...
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... ST92195C/D - I/O PORTS PORT CONTROL REGISTERS (Cont’d) During Reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output Data Register is set to FFh. This condition is also held after Reset, except for Ports 0 and 1 in ROM- less devices, and can be redefined under software control ...
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... BID OUT OUT HI-Z TTL TTL CMOS (or Schmitt (or Schmitt (or Schmitt Trigger) Trigger) Trigger) ST92195C/D - I/O PORTS Bit 0 PxC20 PxC10 PxC00 A/D Pins OUT AF OUT AF IN (1) HI HI-Z TTL TTL TTL ...
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... ST92195C/D - I/O PORTS INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 37. Basic Structure of an I/O Port Pin PUSH-PULL TRISTATE OPEN DRAIN WEAK PULL-UP OUTPUT SLAVE LATCH ALTERNATE FROM FUNCTION PERIPHERAL OUTPUT INPUT OUTPUT BIDIRECTIONAL OUTPUT MASTER LATCH Figure 38. Input Configuration I/O PIN TRISTATE OUTPUT SLAVE LATCH ...
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... Function Output: (Figure 7) – The Output Buffer is turned Open-Drain or Push-Pull configuration. ST92195C/D - I/O PORTS – The data present on the I/O pin is sampled into the Input Latch at the beginning of the execution of the instruction. – The signal from an on-chip function is allowed to load the Output Slave Latch driving the I/O pin. ...
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... GND OUTPUT SLAVE LATCH OUTPUT MASTER LATCH INPUT LATCH INTERNAL DATA BUS ST92195C/D - ALTERNATE FUNCTION ARCHITECTURE 6.5.3 Pin Declared as an Alternate Function Output The user must select the AF OUT configuration using the PxC2, PxC1, PxC0 bits. Several Alter- nate Function outputs may drive a common pin. In ...
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... ST92195C/D - TIMER/WATCHDOG (WDT) 7 ON-CHIP PERIPHERALS 7.1 TIMER/WATCHDOG (WDT) Important Note: This chapter is a generic descrip- tion of the WDT peripheral. However depending on the ST9 device, some or all of WDT interface signals described may not be connected to exter- nal pins. For the list of WDT pins present on the ST9 device, refer to the device pinout description in the first section of the data sheet ...
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... WDTPR register will be effective immediately. End of Count is when the counter is 0. When Watchdog mode is enabled the state of the ST_SP bit is irrelevant. ST92195C/D - TIMER/WATCHDOG (WDT) 7.1.2.4 Single/Continuous Mode The S_C bit allows selection of single or continu- ous mode.This Mode bit can be written with the Timer stopped or running ...
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... ST92195C/D - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 7.1.2.7 Gated Input Mode This mode can be used for pulse width measure- ment. The Timer is clocked by INTCLK/4, and is started and stopped by means of the input pin and the ST_SP bit. When the input pin is high, the Tim- er counts ...
Page 78
... G WD EN=0 WRITE AAh,55h INTO WDTRL PRODUCE COUNT RELOAD ST92195C/D - TIMER/WATCHDOG (WDT) 7.1.3.4 Non-Stop Operation In Watchdog Mode, a Halt instruction is regarded as illegal. Execution of the Halt instruction stops further execution by the CPU and interrupt ac- knowledgment, but does not stop INTCLK, CPU- CLK or the Watchdog Timer, which will cause a System Reset when the End of Count condition is reached ...
Page 79
... ST92195C/D - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 7.1.4 WDT Interrupts The Timer/Watchdog issues an interrupt request at every End of Count, when this feature is ena- bled. A pair of control bits, IA0S (EIVR.1, Interrupt A0 se- lection bit) and TLIS (EIVR.2, Top Level Input Se- lection bit) allow the selection of 2 interrupt sources ...
Page 80
... R249 - Read/Write Register Page: 0 Reset value: 1111 1111b (FFh Bits 7:0 = R[7:0] Counter Least Significant Bits. ST92195C/D - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG PRESCALER REGISTER (WDTPR) R250 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh) 7 PR7 PR6 Bits 7:0 = PR[7:0] Prescaler value. A programmable value from 1 (00h) to 256 (FFh). ...
Page 81
... ST92195C/D - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) Bit 3 = INEN: Input Enable . This bit is set and cleared by software. 0: Disable input section 1: Enable input section Bit 2 = OUTMD: Output Mode. This bit is set and cleared by software. 0: The output is toggled at every End of Count 1: The value of the WROUT bit is transferred to the output pin on every End Of Count if OUTEN=1 ...
Page 82
... Note 2: Depending on device, the source of the INPUT & CLOCK CONTROL LOGIC block may be permanently connected either to STIN or the RCCU signal CLOCK2/x. In devices without STIN and CLOCK2, the INEN bit must be held at 0. ST92195C/D - STANDARD TIMER (STIM) – triggerable input mode, – retriggerable input mode. ...
Page 83
... ST92195C/D - STANDARD TIMER (STIM) STANDARD TIMER (Cont’d) 7.2.2 Functional Description 7.2.2.1 Timer/Counter control Start-stop Count. The ST-SP bit (STC.7) is used in order to start and stop counting. An instruction which sets this bit will cause the Standard Timer to start counting at the beginning of the next instruc- tion. Resetting this bit will stop the counter. ...
Page 84
... Thus the Standard Timer Interrupt uses the interrupt channel and takes the priority and vector of the external inter- rupt channel. ST92195C/D - STANDARD TIMER (STIM) If INTS is set to “1”, the Standard Timer interrupt is disabled; otherwise, an interrupt request is gener- ated at every End of Count. ...
Page 85
... ST92195C/D - STANDARD TIMER (STIM) STANDARD TIMER (Cont’d) 7.2.5 Register Description COUNTER HIGH BYTE REGISTER (STH) R240 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) 7 ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 ST.9 ST.8 Bits 7:0 = ST.[15:8]: Counter High-Byte. COUNTER LOW BYTE REGISTER (STL) R241 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh ...
Page 86
... ST92195C/D - TELETEXT DISPLAY STORAGE RAM INTERFACE 7.3 TELETEXT DISPLAY STORAGE RAM INTERFACE 7.3.1 Introduction The Teletext Display RAM (TDSRAM) is used to hold the Teletext data for display. It can be shared by the following units: – Acquisition Unit (AQD). A buffer containing the teletext data extracted by the slicer from the in- coming Composite Video signal CVBS1. – ...
Page 87
... ST92195C/D - TELETEXT DISPLAY STORAGE RAM INTERFACE TDSRAM (Cont’d) 7.3.2 Functional Description The Teletext Data Storage RAM Interface (TRI) manages the data flows between the different sub- units (display, acquisition, 40-byte buffer, CPU in- terface) and the internal RAM. A specific set of buses (8 bit data TRIDbus, 13 bit address TRIA- bus) is dedicated to these data flows ...
Page 88
... ST92195C/D - TELETEXT DISPLAY STORAGE RAM INTERFACE TDSRAM (Cont’d) Figure 48. Timesharing Slot Configurations Deflection line 1 DIS CPU MBT DIS CPU CPU CPU CPU MBT CPU CPU CPU TXT Acquisition Data unit Slicer MBT 40 bytes ST9 CPU ACQ DIS CPU MBT CPU ...
Page 89
... ST92195C/D - TELETEXT DISPLAY STORAGE RAM INTERFACE TDSRAM (Cont’d) 7.3.2.3 CPU Slowdown on TDSRAM access As described above, the TDSRAM interface puts priority on TV real time constraints and may slow- down the CPU by inserting wait cycles when a TD- SRAM access is requested. The effective duration ...
Page 90
... ST92195C/D - TELETEXT DISPLAY STORAGE RAM INTERFACE TDSRAM (Cont’d) 7.3.3 Initialisation 7.3.3.1 Clock Initialisation Before initialising the TRI, first initialise the pixel clock. Refer to the Application Examples in the OSD chapter and to the RCCU chapter for a de- scription of the clock control registers. 7.3.3.2 TRI Initialisation ...
Page 91
... ST92195C/D - TELETEXT DISPLAY STORAGE RAM INTERFACE TDSRAM (Cont’d) 7.3.4 Register Description 7.3.4.1 Data Registers BUF0..15 R240 .. R255 Page 36Read/Write RAM Buffer Data Register x = 0,..,15 BUF16..31 R240 .. R255 Page 37 Read/Write RAM Buffer Data Register x = 16,..,31 BUF32..39 R240 .. R247Page 38 Read/Write RAM Buffer Data Register x = 32,..,39 ...
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... ST92195C/D - TELETEXT DISPLAY STORAGE RAM INTERFACE TDSRAM (Cont’d) 7.3.4.3 Control Registers RAM BUFFER CONTROL REGISTER (BUFC) R248 - Read/Write Register Page: 38 Reset Value: 0000 1000 (08h PEF BADU MOD2 MOD1 MOD0 BUSY Bits 7:6 = Reserved, keep in reset state. Bit 5 = PEF: Parity Error Flag . ...
Page 93
... ST92195C/D - TELETEXT DISPLAY STORAGE RAM INTERFACE TDSRAM (Cont’d) RAM INTERFACE CONFIGURATION REGIS- TER (CONFIG ) R252 - Read/Write Register Page: 38 Reset Value: 0000 0110 (06h Bits 7:4 = Reserved, keep in reset state. Bit 3 = DS: Double Scan When the DS bit is reset, the TDSRAM interface and the CSYNC controller behave in 50Hz/60Hz compatible mode ...
Page 94
... Fast Blanking switching signal through four analog outputs. The three Color outputs use a 3-level DAC which can generate half-intensity col- ors in addition to the standard saturated colors. ST92195C SCREEN DISPLAY (OSD) The Display block diagram is shown on on page 96. A smart pixel processing unit provides enhanced features such as rounding or fringe for a better pic- ture quality ...
Page 95
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Serial character attributes: – Foreground Color (8 possibilities in Serial Full page display mode) – Background Color (8 possibilities) – Flash / Steady – Start Box / End Box – Double height – Conceal / display – Fringe – Contiguous Mosaic / Separated Mosaic – ...
Page 96
... Scroll 1 Row CONTROL Gen PLA Cmd MOSAIC PLA Shift Register (10b) L1/L1+ mux Char Decoding Character Code RAM INTERFACE ST92195C SCREEN DISPLAY (OSD) RAM INTERFACE Gen RAM Add Char Counter Comp VPOS Comp HPOS Pixel Counter CURSOR CONTROL Gen ROM Add PIXEL ...
Page 97
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.3 Functional Description 7.4.3.1 Screen Display Area The screen is divided in 26 rows of basically 40 characters. From row 1 to row 23 possible to display 80 characters per row with the following re- strictions: – Serial mode only – No rounding or fringe Figure 50 ...
Page 98
... All character matrix contents are fully user de- finable and are stored in the pixel ROM (except the G1 mosaic set which is hardware defined). ST92195C SCREEN DISPLAY (OSD) A set of colors defines the final color of the current pixel. In general, the character matrix content is dis- ...
Page 99
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Figure 52. Display Character Scheme ROUNDING MODE Background Foreground Smooth Rounding Figure 53. Rounding and Fringe Effects Dot (four pixels) Added pixel Smooth Rounding Effect 99/249 NORMAL MODE FRINGE MODE Underline Added pixel Global Rounding Effect ...
Page 100
... Parallel Mode 0 = Full Page Mode (Default) 23 lines plus 1 header and two status lines. Page or Line Display Mode (PM) 1= Line Mode ST92195C SCREEN DISPLAY (OSD) Cursor Control Scrolling Control 7.4.4.1 Global Attributes These global attributes are defined through their corresponding registers (see the Register Descrip- tion) ...
Page 101
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Table 19. Global Attributes (Cont’d) Global Attributes Box Control ModeText In/ Text In/ Text Out Box configurable with 3 bits. Refer to FSCCR register de- Out scription for details. Refer to the register description for bit settings. Active on the whole page, ...
Page 102
... CKPIX LINE 4 NORMAL DISPLAY CKPIX Figure 55. Translucent Display Scheme CKPIX R, G, B(40c) FB TSLU ST92195C SCREEN DISPLAY (OSD) Fringe Solid Background Solid Foreground + Rounding Video LINE 3 SEMI TRANSPARANT DISPLAY CKPIX LINE 4 SEMI TRANSPARANT DISPLAY CKPIX ...
Page 103
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Figure 56. Half-Tone Display Scheme VIDEO PROCESSOR Internal Red Contrast Internal Green Reduction Internal Blue HT ST9 MCU 7.4.4.2 Row Attributes The header and status row attributes are set using the HSCR R244 (F4h) Page 32 register. The row enable bits as set in registers DE0R ...
Page 104
... ALWAYS active (even in Full Page Serial Mode, i.e. for Text Level 1) (4) Toggles action if the Fringe Enable is set (bit 5 in register DCM0R R250 (FAh) Page 32. Selects a second G0 if the Switch Enable bit is set (bit 5 in register NCSR R245 (F5h) Page 32) ST92195C SCREEN DISPLAY (OSD) FLASHING Z ...
Page 105
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Flash: (/= Steady) The next characters are dis- played with the foreground color alternatively equal to background and foreground on a period based on Vsync (32 Vsync: foreground, 16 Vsync: background) until a Steady serial attribute. Fringe: If the Fringe Enable bit is set in the global ...
Page 106
... Rows displayed in serial mode Display Memory Location ST92195C SCREEN DISPLAY (OSD) TEXT inside box is visible* < > Propagation Length of row = 40 Characters < > BO BOX-OFF attribute BOX-ON attribute ...
Page 107
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.4.3 Parallel Attributes Figure 61. Example of Row in Parallel Mode Display Default foreground Default background global Attributes Location Characters Location Each character is defined on 2 bytes in Parallel Mode (see Figure 61 on page 107.) Parallel Mode is selected by setting the SPM bit in the DCM1R register R251 (FBh) Page 32 ...
Page 108
... Figure 62. Parallel Color and Shape Attributes Attribute location Character A location A ST92195C SCREEN DISPLAY (OSD) Only for Background. Color mode of parallel attributes G2-Menu characters or G1/Extended menu charac- ters selection mosaic Dual function depending on character code The character is 20 pixels high The character is 20 pixels wide. Available in Parallel mode or in Line mode ...
Page 109
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.4.4 Font Selection using Parallel Attributes Parallel attributes have an immediate effect. They are applied to the associated character. These at- tributes can also have a “serial” effect, the defined attribute being still defined on the following charac- ters: this is known as attribute propagation ...
Page 110
... Secondary effects can be generated when the shape format is not respected. The 3 figures below describe the combination of parallel size attributes to obtain the different char- acter sizes: · Double Width · Double Height · Double Size ST92195C SCREEN DISPLAY (OSD) RAM content in Parallel Mode ...
Page 111
... ST92195C SCREEN DISPLAY (OSD) Figure 64. Double Width Examples Double width Double width Attributes location Characters location 1 ROW 7.4.4.7 Example of using Double Height Attribute In parallel mode, Double Height characters can be obtained as follows. The Double Height attribute concerns two consecutive rows. Repeat the char- Figure 65 ...
Page 112
... In parallel mode, the Underline mode on character can be obtained simply by setting the bit 1 ‘US’ of the shape attribute. To underline double height ST92195C SCREEN DISPLAY (OSD) be repeated on the two rows. Bits 2 and 3 of the shape attribute must be set on the two locations. In addition bit 4 must be set or reset to define the top or bottom half-character ...
Page 113
... ST92195C SCREEN DISPLAY (OSD) Figure 67. Underline Example Display Attribute location Underline (US=1) Character location 7.4.4.10 Attribute Rules The default colors for foreground and background are defined through the register DCR R240 (F0h) Page 33. A display defined in parallel mode can accept a se- rial color attribute, and propagation is available un- til a new color attribute (serial or parallel) is en- countered ...
Page 114
... Scrolling Control Low R248 (F8h) Page 32 – Scrolling Control High R249 (F9h) Page 32 7.4.5.1 RGB & FB DAC and TSLU Outputs The RGB and FB pins of the ST92195C/D are an- alog outputs controlled by true Digital to Analog Converters. These outputs are specially designed to directly drive the Video Processor. ...
Page 115
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.6 Display Memory Mapping Examples The display content is stored in TDSRAM bytes starting at address 8000h). Use register TDPR R252 (FCh) Page 32 to address the memo- ry blocks containing the display data. Two 4-bit ad- dress pointers (bits PG and HS) must be given that point to separate blocks containing the display page and the header/status rows ...
Page 116
... Status Row 0 Attr. Status Row 1 Attr. Free Space Resolution 0.5K bytes ST92195C SCREEN DISPLAY (OSD) Header & Status Rows Location The 0.5 Kbyte block containing the Header, Status Row 0 and Status Row 1 is pointed to by the HS3..HS0 bits. The Header/Status attributes are stored in this block at offset 80h ...
Page 117
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.6.3 Building a Serial Mode, 40-Char, Line Mode Display Half-Page Location The 0.5 Kbyte block of half-page content is stored in the TDSRAM location pointed to by the PG3..PG0 bits. Figure 73. Serial (40 Characters) Line Mode Mapping 0.5K TDSRAM Block Row 1 Number (0 ...
Page 118
... Row 12/Scrolling Buffer Free Space Resolution 1K bytes See Figure 69 on page 115 ST92195C SCREEN DISPLAY (OSD) Header & Status Rows Location The 0.5 Kbyte block containing the Header, Status Row 0 and Status Row 1 is pointed to by the HS3..HS0 bits. The Header/Status attributes are stored in this block at offset 80h ...
Page 119
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.6.5 Building a Serial Mode, 80 Char, Full Page Display Half-Page Location The pair of adjacent 1 Kbyte blocks of page con- tent is stored in the TDSRAM location pointed to by the PG3..PG0 bits. The first block contains the left side of the page, the second block contains the right side of the page ...
Page 120
... Status Row 1 Free Space Row Attr. Free Space Resolution 0.5K bytes ST92195C SCREEN DISPLAY (OSD) Header/Status Rows Location The 0.5 Kbyte block containing the Header, Status Row 0 and Status Row 1 is pointed to by the HS3..HS0 bits. The Row attribute (row count) is stored in this block at offset 100h and contains 12 bytes for line mode (see DCM1R register description) ...
Page 121
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.7 Font Mapping The font consists of two character sets of 512 characters each. Only one set can be accessed at the same time. The FRSW bit of the NCSR regis- ter allows to switch from one set to the other. ...
Page 122
... PARALLEL MODE ATTRIBUTES (PS=x, CSS=0) (32 CODES) Char. Codes 0 1F Addresses 100 11F SERIAL PARALLEL MODE ATTRIBUTES (PS=1, CSS=1) (32 CODES) Char. Codes 0 1F ST92195C SCREEN DISPLAY (OSD) 6th 7th 5Dh 5Eh 13th 7Eh 7F 80 (96 CODES) G1* (32 *If Serial Attributes 19, 1A are used 7F 80 (96 CODES) 7F ...
Page 123
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) Table 26. Single G0 Mode - Font Mapping ROM Address Character Code 000h to 01Fh 0E0h to 0FFh 020h to 07Fh 020h to 07Fh 080h to 0FFh 080h to 0FFh 100h to 10Ch (see table below) 10Dh to 119h (see table below) 11Ah to 126h ...
Page 124
... ON SCREEN DISPLAY (Cont’d) Figure 79. Pan-European Font (East/West) Character Codes (Hex.) National Character Subset 0 Figure 80. OSD Picture in Parallel Mode ST92195C SCREEN DISPLAY (OSD) Extended Menu G0_0 G2-Menu National Char. Subsets 1..14d Extended Menu 124/249 ...
Page 125
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY(Cont’d) 7.4.9 Register Description HORIZONTAL BLANK REGISTER (HBLANKR) R240 - Read/Write Register Page: 32 Reset Value: 0000 0011 (03h) 7 HB7 HB6 HB5 HB4 HB3 It controls the length of the Horizontal Blank which follows the horizontal sync pulse. Bits 7:0 = HB[7:0]: The horizontal blank period is calculated with a pixel down counter loaded on each Hsync by HB[7:0] ...
Page 126
... Text inside box with transparent background Text outside box with solid background ST92195C SCREEN DISPLAY (OSD) Bit 4 = HTC: Half-Tone/Translucency Control Bit This bit allows the selection of TSLU al- ternate function output. 0: TSLU is selected as I/O pin alternate function selected as I/O pin alternate function ...
Page 127
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) HEADER & STATUS CONTROL REGISTER (HSCR) R244 - Read/Write Register Page: 32 Reset Value: 0010 1010 (2Ah ES1 NS1 ES0 Bits 7:6 = Reserved. Bits 5,3 = ES[1:0]: Enable Status Rows [1:0] dis- play control bits. If the bit is reset, the correspond- ing Status Row is filled with the full screen color ...
Page 128
... If SWE is reset, the used G0 alphabet is pointed through NC[1:0]. If SWE is set, the used G0 alphabet is pointed through NC[3:2] and NC[1:0] toggled by 1Bh serial attribute. ST92195C SCREEN DISPLAY (OSD) Bit 4 = NCM: National Character Mode control bit. This bit reconfigures a part of the font set as defin- ing: – either a single G0 alphabet with national sub-sets, – ...
Page 129
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) CURSOR HORIZONTAL POSITION REGISTER (CHPOSR) R246 - Read/Write Register Page: 32 Reset Value: 0000 0000 (00h CHP6 CHP5 CHP4 CHP3 CHP2 CHP1 CHP0 Bit 7 = Reserved. Bits 6:0 = CHP[6:0]: Cursor Horizontal Position . The cursor is positioned by character. ...
Page 130
... ST92195C SCREEN DISPLAY (OSD) REGISTER Bit 6 = FSC: Freeze scrolling Note: The 2 control bits SCE and FSC must be set to "1" before enabling the Global double height (see the DH bit in the SCHR register). Bit 5 = SS: Scrolling Speed Control bit. ...
Page 131
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) SCROLLING CONTROL HIGH (SCHR) R249 - Read/Write Register Page: 32 Reset Value: 0000 0000b (00h EER UP/D LRS4 LRS3 LRS2 Bit 7 = DH: Global Double Height control bit . This bit must only be used in Page Mode. When ...
Page 132
... ROW D ROW B ROW VSYNC ROW D ROW A ROW VSYNC ROW C ROW First row to scroll C= Last row to scroll E= Extra row ST92195C SCREEN DISPLAY (OSD) Freeze on New TDSRAM address after 5 Vsync after EER=1 ROW A ROW A ROW B ROW B ROW C ROW C EER=0 ROW A ...
Page 133
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) DISPLAY CONTROL MODE (DCM0R) R250 - Read/Write Register Page: 32 Reset Value: 0000 0000 (00h STE FRE CE GFR Bit 7 = DE: Display Enable control bit . reset, no display will be performed set, a display will be done as defined through the various control bits ...
Page 134
... TDSRAM will be displayed as the 6th row on the screen. Bit 0 = SPM: Serial/Parallel Mode control bit . If the SPM bit is reset, the display is done in Serial ST92195C SCREEN DISPLAY (OSD) 1 REGISTER mode, i.e. a character or attribute is coded with a single byte. If the SPM bit is set, the display is done in Parallel mode, i ...
Page 135
... ST92195C SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) DISPLAY ENABLE 0 CONTROL REGISTER (DE0R) R253 -Read/Write Register Page: 32 Reset Value: 1111 1111 (FFh Bits 7:0 = R[8:1]: Row display enable control bit . When the “Ri” bit is set (Reset value), the corre- sponding row (with row in the page, numbered from 1 to 23) will be displayed. When the “ ...
Page 136
... ACP4 ACP3 ACP2 ACP1 ACP0 Bits 7:5 = Reserved, keep in reset state. Bits 4:0 = ACP[4:0]: Absolute Vertical Position of the cursor in case of double height or scrolling. ST92195C SCREEN DISPLAY (OSD) TDSRAM PAGE POINTER REGISTER (TDPPR) R246 - Read/Write Register Page: 33 Reset Value: xxx0 0000 (x0h ...
Page 137
... ST92195C SCREEN DISPLAY (OSD) 7.4.10 Application Software Examples Before starting an OSD Display very important to start all the internal clock/timings To understand the software routines given below, make a thorough study of the chapters on the Reset and Clock Control Unit (RCCU) and the TDSRAM Interface. ...
Page 138
... F5, National Characters register ld NC, #010h; SWE, NCM, NC[3:0] ;------- Scrolling INIT ---------- spp #DMP1_PG; page 020h Display memory map registers page ST92195C SCREEN DISPLAY (OSD) start Pixel Line PLL ; no subtitle mode ...
Page 139
... ST92195C SCREEN DISPLAY (OSD) ; F8, Scrolling Control Line register ld SCLR ,#000h ; SCE, FSC, SS, FIRSTROWSCRO[4:0] ; F9, Scrolling Control Horizontal register ld SCHR ,#02fh ; DH, ER, UP/D, LASTROWSCRO[4:0] ;------- Cursor position ; F8, Scrolling Control Line register ld SCLR ,#000h ; SCE, FSC, SS, FIRSTROWSCRO[4:0] ; F9, Scrolling Control Horizontal register ld SCHR ,#02fh ; DH, ER, UP/D, LASTROWSCRO[4:0] ; F6, Cursor Horizontal Position register ld CHPOSR , #005h ...
Page 140
... VDLY VPOL VSEP HSF(3:0) SCCS0 Register ST92195C/D - SYNC CONTROLLER sharing by the Teletext Acquisition, the Display Controller and the CPU (for more details refer to the TDSRAM Controller chapter). Field informa- tion is also available for the Display Controller. The SYNC Controller unit also generates two in- terrupt sources corresponding respectively the TV field start and to the end of VBI event (“ ...
Page 141
... ST92195C/D - SYNC CONTROLLER SYNC CONTROLLER (Cont’d) 7.5.1 H/V Polarity Control Two control bits manage the H/V polarities. HPOL (SCCS0R.6) manages the HSYNC polarity (a pos- itive polarity assumes the leading edge is the ris- ing one). VPOL (SCCS0R.7) controls the VSYNC polarity. 7.5.2 Field Detection Field detection is necessary information for the Display controller for fringe and rounding features ...
Page 142
... TXTOUT ST92195C/D - SYNC CONTROLLER The CSYNC signal characteristics are assumed to perfectly respect the STV2160 TXTOUT pin spec- ification which is reviewed in The vertical sync signal is extracted from the CSYNC signal by the mean of an Up/Down coun- ter used as a digital integrator. The counter works in “ ...
Page 143
... ST92195C/D - SYNC CONTROLLER SYNC CONTROLLER (Cont’d) 7.5.4.3 Free-Running Monitor Sync Mode This mode is accessed when the MOD1 bit is set. In this mode, the chassis HSYNC and VSYNC sig- nals are not used. They are replaced by the sync signals which are fully Crystal based (use of the in- ternal main 4 MHz Clock) ...
Page 144
... Bit 6= HPOL. HSYNC/CSYNC Polarity . 0: Negative polarity (leading edge is falling edge) 1: Positive polarity (leading edge is rising edge) ST92195C/D - SYNC CONTROLLER Bit 5= VSEP. Separate Sync This bit selects either HSYNC/VSYNC or CSYNC synchro controller mode only valid when MOD[1:0] are reset: 0: The standard mode using two inputs (VSYNC and HSYNC) is activated. 1: The Composite Sync mode is activated ...
Page 145
... ST92195C/D - SYNC CONTROLLER SYNC CONTROLLER (Cont’d) SYNC CONTROLLER CONTROL AND STATUS REGISTER 1 (SCCS1R) R243 - Read/Write Register Page: 35 Reset value: 0000 0000 (00h) 7 EOFVBI FLDST FLDEV HFLG FSTEN VBIEN MOD1 MOD0 Bit 7= EOFVBI: End Of VBI Flag . This bit is set to “1” by hardware at the beginning of the line 25 of the current field, when the End of VBI interrupt request is sent to the Core ...
Page 146
... Figure 86. Time Windowing for Slicers n SYNC Extractor CVBS1 Analog Front-End ST92195C/D - SYNC EXTRACTOR updated at each beginning of field. In case a field start is missed, the field detection flag will keep toggling according to its previous value and the end of field predicted by the line counter (312 or 313 lines). ...
Page 147
... ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT 7.7 TELETEXT SLICER AND ACQUISITION UNIT 7.7.1 Introduction The Teletext Slicer processes the incoming Com- posite Video signal (CVBS1 pin) to extract Teletext data. The Acquisition Unit filters the data flow from the slicer and transfers valid line data to the acquisi- tion buffer where it is read by the TDSRAM inter- face ...
Page 148
... Figure 88. CVBS1 Functional Description n CVBS1 TXTGC(1:0) VBGP ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT The composite video signal enters the Sync Ex- tractor through the CVBS1 pin. The sync pulse’s peak value (with reference to black level) is stored. This signal's pulse amplitude (VDETB) is then fed to channel 0 of the A/D converter ...
Page 149
... ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT TELETEXT SLICER AND ACQUISITION UNIT (Cont’d) 7.7.3.2 Signal Windows TXTEN (TXSCR.7) is the Teletext Enable bit. Set- ting this bit allows the slicer to check for the pres- ence of Teletext data. The search for data is from line 6 to line 22 for field 1 and from line 318 to line 335 for field 2 ...
Page 150
... TELETEXT SLICER AND ACQUISITION UNIT (Cont’d) Figure 90. Acquisition Unit Block Diagram ACQ. Command Multiplexer Async r h onism Control Shift Register FRAMING Comparator ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT Tel. Data 8 bits Acq. New Byte Enable Acq. Write Enable RAM Data ...
Page 151
... ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT TELETEXT SLICER AND ACQUISITION UNIT (Cont’d) 7.7.4.1 Data Extraction and Synchronization Teletext data extraction is based on synchroniza- tion signals from the CVBS1 input video composite signals (Hcvbs and Vcvbs). Teletext data storage into the internal TDSRAM is ...
Page 152
... This de- cision is then kept until the end of the 41 bytes ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT flow, generating a "write enable" flag which is for- warded to the Data Storage Unit. The content of the Data Storage Unit is then trans- ferred to a TDSRAM memory area called " ...
Page 153
... ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT TELETEXT SLICER AND ACQUISITION UNIT (Cont’d) Page Handler The page handler controls all packet types other filtered than those already mentioned (i.e. packets X/0 to X/28).These packets are filtered magazine- wise by the Acquisition Unit. Two registers, called “Page Opened” Register (ACQPOR) and “ ...
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... ACQWEN line is reset and no TDSRAM write is al- lowed. The TDSRAM interface will perform a read operation to the TDSRAM; for more details, refer to the TDSRAM interface specification. ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT 7.7.4.3 Address Generation The address generation unit provides to the TDSRAM interface the real time address where the byte must be stored into the internal TDSRAM ...
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... ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT TELETEXT SLICER AND ACQUISITION UNIT (Cont’d) 7.7.5 Hamming Decoding The Hamming Decoding Unit is a separate block that the application software can use to check and decode Hamming coded data groups of three bytes (Hamming 24/18 format) or one data byte (Hamming 8/4 format) ...
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... ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT Equation ( = xor Handling b erroneous corrected 1 b erroneous corrected 7 b erroneous corrected ...
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... ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT TELETEXT SLICER AND ACQUISITION UNIT (Cont’d) 7.7.6 Teletext Signal Quality Measure In order to determine the quality level of the re- ceived CVBS Teletext signal, the following infor- mation is provided to the CPU through the Teletext signal Quality Measure register, called “AC- QTQM” ...
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... Page closed, wait for new header 0 1 Page opened. Storage ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT ACQUISITION NEW HEADER RECEIVED REG- ISTER (ACQNHRR) R250 - Read/Write Register Page: 34 Reset value: 0000 0000 (00h NHR7 NHR6 NHR5 NHR4 NHR3 NHR2 NHR1 NHR0 Each bit in the ACQNHR register corresponds to a magazine ...
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... ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT TELETEXT SLICER AND ACQUISITION UNIT (Cont’d) ACQUISITION PACKET REQUEST REGISTER (ACQPRR) R251 - Read/Write Register Page: 34 Reset value: 0xxx 0000 (00h) 7 HAMF - FR7B FRDET SPF Bit 7 = HAMF: Hamming Check mode control. This bit is set and cleared by software. ...
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... ACQUISITION HAMMING DECODING REGIS- TER 1 (ACQHD1R) R254 - Read/Write Register Page: 34 Reset value: xxxx xxxx (xxh) 7 HDE15 HDE14 HDE13 HDE12 HDE11 HDE10 HDE9 HDE8 ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT ACQUISITION HAMMING DECODING REGIS- TER 0 (ACQHD0R) R255- Read/Write Register Page: 34 Reset value: xxxx xxxx (xxh) 0 ...
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... ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT TELETEXT SLICER AND ACQUISITION UNIT (Cont’d) Hamming 24/18 Correction On writing, these 24 bits are the data to be Ham- ming 24/18 checked, where “P” are Hamming bits and “D” are Data bits. ACQHD2R 23 P6 D18 D17 ...
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... D are Data bits. HDE[23:8]: don't care. ACQHD2R ACQHD1R ACQHD0R ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT On reading, the bits are redefined as follows: ACQHD2R ACQHD1R ACQHD0R ...
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... ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT TELETEXT SLICER AND ACQUISITION UNIT (Cont’d) The ACQAD1R, ACQAD0R registers are 2 read/ write registers that define the current address val- ue bits as follows: ACQUISITION ADDRESS (ACQAD1R) R242 - Read/Write Register Page: 34 Reset value : 000x xxxx (xxh) ...
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... Teletext front-end Slicer an amplified CVBS sig- nal, the gain being defined by the TXTGC(1:0) bits of the Teletext Slicer Control Register (TX- SCR). 1: Pre-amplifier is by-passed. ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT Bit 1 = Reserved bit, keep in reset state. Bit 0 = ADCSEL: ADC Selection. This bit is set and cleared by software to choose 0 which analog signal is sent to the A/D converter channel 0 ...
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... ST92195C/D - VPS & WSS SLICER 7.8 VPS & WSS SLICER 7.8.1 Introduction The VPS/WSS digital sections perform several functions: Separate the horizontal and vertical sync signals Determine the field and line information (in conjunction with the Sync Extractor) Figure 92. VPS/WSS Block Diagram n VSync CK @5MHz ...
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... The average amplitude is ac- complished by AC coupling the video input signal ST92195C/D - VPS & WSS SLICER into the slicer cell and gating the bias circuits dur- ing the active bi-phase signal. ...
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... ST92195C/D - VPS & WSS SLICER VPS & WSS SLICER (Cont’d) 7.8.3 About Video Programming System (VPS) The VPS extracts the digital data from line transmitted PAL video signal. The VPS feature for the VCR uses only 5 of the 13 bytes of information to help simplify the programming of the VCR for re- cording ...
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... The signal consists of 000111100011110000011111 clock. ST92195C/D - VPS & WSS SLICER If the start code is not recognised 14.3 +/- 0.2 µs after the WSSWin rising edge, the system waits for the next WSSWin to find a Start code. Data Bits Purpose Bi-phase Encoding Dura- tion(1.2 Data Group 1 Bits: ...
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... ST92195C/D - VPS & WSS SLICER VPS & WSS SLICER (Cont’d) 7.8.6 WSS Data Group Assignments The 14 data bits of the WSS signal are divided into 4 groups. Group 1 contains 4 bits in which the first 3 carry data and the last bit is the odd parity bit for the first three bits ...
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... Bit 0 = ERB1: Error in Byte for VPSD0R (R/W) Data was written but a bi-phase error was detect- ed. Set by hardware when there is an error. The user must reset it by software ST92195C/D - VPS & WSS SLICER VPS DATA REGISTER 0 (VPSD0R) R241 - Read Only Register Page: 6 Reset value: 0000 0000 (00h) ...
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... ST92195C/D - VPS & WSS SLICER VPS & WSS SLICER (Cont’d) VPS DATA REGISTER 3 (VPSD3R) R244 - Read Only Register Page: 6 Reset value: 0000 0000 (00h) 7 ASM5 ASM4 ASM3 ASM2 ASM1 ASM0 Bit 7:2 = ASM[5:0]: Announced start of item, MINUTE . Bit 1:0 = NC[3:2]: Nationality code which is used to identify the source of the item ...
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... SLCCR register is set (refer to the Timing and Clock Controller Chapter), i.e. when the PLL is en- abled. ST92195C/D - VPS & WSS SLICER Bit 3 = WINDLY: Window Delay Bit This bit is common to VPS and WSS. Due to the large range of signals in VPS mode (data start be- ...
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... ST92195C/D - VPS & WSS SLICER VPS & WSS SLICER (Cont’d) DUPLICATE WSS DATA AND STATUS REGIS- TER (WSSDS4R) R251- Read Only Register Page: 6 Reset value: 0000 0000 (00h) 7 WSS2X x x GP2ERF2 WSS2(7) WSS2(6) WSS2(5) WSS2(4) Bit 7 = WSS2X: WSS has been received 2X (2 times) ...
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... SPEN BMS ARB BUSY CPOL CPHA SPR1 SPR0 SERIAL PERIPHERAL CONTROL REGISTER ( SPICR ) ST9 INTERRUPT INTB0 * Common for Transmit and Receive n ST92195C/D - SERIAL PERIPHERAL INTERFACE (SPI) Master operation only 4 Programmable bit rates Programmable clock polarity and phase Busy Flag End of transmission interrupt ...
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... ST92195C/D - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 7.9.3 Functional Description The SPI, when enabled, receives input data from the internal data bus to the SPI Data Register (SPIDR). A Serial Clock (SCK) is generated by controlling through software two bits in the SPI Control Register (SPICR). The data is parallel loaded into the 8 bit shift register during a write cy- cle ...
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... PORT BIT LATCH PORT BIT LATCH INT2 ST92195C/D - SERIAL PERIPHERAL INTERFACE (SPI) 7.9.4 Interrupt Structure The SPI peripheral is associated with external in- terrupt channel B0 (pin INT2). Multiplexing be- tween the external pin and the SPI internal source is controlled by the SPEN and BMS bits, as shown in ...
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... ST92195C/D - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 7.9.5 Working With Other Protocols The SPI peripheral offers the following facilities for 2 operation with S-bus/I C-bus and IM-bus proto- cols: Interrupt request on start/stop detection Hardware clock synchronisation Arbitration lost flag with an automatic set of data ...
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... Figure 97. SPI Data and Clock Timing (for I2C protocol) 1st BYTE SDA SCL 1 2 FOR ACKNOWLEDGEMENT START CONDITION n ST92195C/D - SERIAL PERIPHERAL INTERFACE (SPI) Software Hardware SCK, SDO in HI-Z SCL, SDA = 1, 1 SDA = 0, SCL = 1 interrupt request SCL = 0 Start transmission Interrupt request at end of byte transmission ...
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... ST92195C/D - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) The data on the SDA line is sampled on the low to high transition of the SCL line. 2 SPI working with an I C-bus 2 To use the SPI with the I C-bus protocol, the SCK line is used as SCL; the SDI and SDO lines, exter- nally wire-ORed, are used as SDA ...
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... SEN START n Figure 100. S-bus Configuration n ST92195C/D - SERIAL PERIPHERAL INTERFACE (SPI) SPI Working with S-bus 2 C- The S-bus protocol uses the same pin configura- tion as the I SDA lines. The additional SEN line is managed through a standard ST9 I/O port line, under soft- ...
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... ST92195C/D - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 7.9.8 IM-bus Interface The IM-bus features a bidirectional data line and a clock line; in addition, it requires an IDENT line to distinguish an address byte from a data byte 2 ure 101). Unlike the I C-bus protocol, the IM-bus protocol sends the least significant bit first; this re- ...
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... CPOL CPHA Bit 7 = SPEN: Serial Peripheral Enable . 0: SCK and SDO are kept tristate. ST92195C/D - SERIAL PERIPHERAL INTERFACE (SPI) 1: Both alternate functions SCK and SDO are ena- bled. Note: furthermore, SPEN (together with the BMS bit) affects the selection of the source for interrupt channel B0 ...
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... ST92195C/D - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) Bit 2 = CPHA: Transmission Clock Phase. CPHA controls the relationship between the data on the SDI and SDO pins, and the clock signal on the SCK pin. The CPHA bit selects the clock edge used to capture data ...
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... Master Operation – 4-bit Frequency Control register to select clock frequencies for the SCL line ranging from ST92195C/D - TWO-CHANNEL I 20 kHz to 800 kHz derived from a 4MHz crystal clock – Compatible with standard 7 or extended 10-bit address protocol – ...
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... ST92195C/D - TWO-CHANNEL BUS INTERFACE (Cont’d) 7.10.2 General Description In addition to receiving and transmitting data, this interface convert them from serial to parallel for- mat and vice versa. The interface is connected, 2 through a multiplexer, to one I C bus among data pin, SDAx, and by a clock pin, SCLx, where x range value ...
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... SDA 2 SCL 2 SCL In CLOCK GENERATION UNIT ST92195C/D - TWO-CHANNEL I Then, select one of the two buses available and configure the corresponding pins to the alternate function (refer to the I/O port chapter). Depending on your application, you may use the advanced features (see the UNPROC and UNEXP bits of the I2CSTR2 register) by setting the AFEN bit of the I2CCTR register ...
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... ST92195C/D - TWO-CHANNEL BUS INTERFACE (Cont’d) 7.10.3.2 Slave Mode As soon as a start condition is detected, the ad- dress is received from the SDA line and sent to the shift register; then it is compared with: – The 7 MSB of the interface address (see I2COAR register) if the ADR0 bit = 0 – ...
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... I2CSTR2 register. The user can check the ACK_BIT bit of the I2CSTR1 register in order to handle the transac- tion properly. ST92195C/D - TWO-CHANNEL I Closing a master communication The master interface will generate a stop condition on the bus when the user sets the STOP bit of the I2CSTR1 register ...
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... ST92195C/D - TWO-CHANNEL BUS INTERFACE (Cont’d) 7.10.6 Register Description OWN ADDRESS REGISTER (I2COAR) R240 - Read/Write Register Page: 44 Reset Value: 0000 0000(00h) 7 ADR7 ADR6 ADR5 ADR4 ADR3 Bit 7:1 = ADR[7:1] Interface Slave Address These bits are the 7 most significant bits of the 8- bit address assigned to interface when it works in slave mode ...
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... In push-pull mode, the frequency values present the following table correspond to an approxi- mate frequency assuming that : ST92195C/D - TWO-CHANNEL I – the first data bit is transferred at a lower frequen- cy (clock stretching capability), – the acknowledge bit is transferred at the slave speed without push-pull mode, 0 – ...
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... ST92195C/D - TWO-CHANNEL BUS INTERFACE (Cont’d) CONTROL REGISTER (I2CCTR) R242 - Read/Write Register Page: 44 Reset Value: 0000 0001(01h) 7 GENC_ SEND_ MONI AFEN RTI ACK ACK TOR Bit 7 = AFEN Advanced Features Enable bit This bit enables or disables the unexpected & un- processed error detection ...
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... Checking the ACTIVE bit (in the I2CSTR1 register) allows to correctly identify an interrupt generated by a stop condition. ST92195C/D - TWO-CHANNEL I Bit 6 = SFEN Spike Filter Enable bit This bit enables or disables the spike filters on the SDAx and SCLx inputs ( 2). ...
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... ST92195C/D - TWO-CHANNEL BUS INTERFACE (Cont’d) Bit 1 = UNEXP Unexpected flag bit This bit is useful for error detection in a multimas- ter mode system, when a master is continuing its transaction while an other concurrent master wants to finish or restart a transaction by sending a “Start” “Stop” condition. ...
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... Note: the FIRST bit is automatically cleared at the end of the interrupt, after the address, and when the interface returns into inactive slave state. ST92195C/D - TWO-CHANNEL I Bit 3 = GEN_CALL General CALL status bit This bit indicates if a general call has been detect the bus. ...
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... ST92195C/D - TWO-CHANNEL BUS INTERFACE (Cont’d) Table 35. I2C Interface Register Map and Reset Values Register Address 7 Name I2COAR 240 ADR7 Reset Value I2CFQR 241 BUS_S0 Reset Value I2CCTR 242 AFEN Reset Value I2CDR 243 SR8 Reset Value I2CSTR2 244 ...
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... MHz internal system clock Analog Inputs (the number of inputs is device dependent, see device pinout) Figure 106. A/D Converter Block Diagram n DATA REGISTER ST92195C/D - A/D CONVERTER (A/D) Single/Continuous Conversion Mode External/Internal synchronization) Power Down mode (Zero Power Consumption) 1 Control Logic Register 1 Data Register 7 ...
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... ST92195C/D - A/D CONVERTER (A/D) A/D CONVERTER (Cont’d) The conversion technique used is successive ap- proximation, with AC coupled analog fully differen- tial comparators blocks plus a Sample and Hold logic and a reference generator. The internal reference (DAC) is based on the use of a binary-ratioed capacitor array. This technique allows the specified monotonicity (using the same ratioed capacitors as sampling capacitor) ...
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... INTCLK (11.5µs at INTCLK = 12 MHz) Note: Fast conversion mode is only allowed for in- ternal speeds which do not exceed 12 MHz. Bit 3 = TRG: External/Internal Trigger Enable . ST92195C/D - A/D CONVERTER (A/D) This bit is set and cleared by software. 0: External/Internal Trigger disabled. 1: Either a negative (falling) edge on the EXTRG pin Chip Event writes a “1” into the STR bit, enabling start of conversion ...
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... ST92195C/D - A/D CONVERTER (A/D) A/D CONVERTER (Cont’d) A/D CHANNEL i DATA REGISTER (ADDTR) R240 - Read/Write Register Page: 62 Reset value: undefined 7 R.7 R.6 R.5 R.4 R.3 The result of the conversion of the selected chan- nel is stored in the 8-bit ADDTR, which is reloaded with a new value every time a conversion ends. Bits 7:0 = R[7:0]: Channel i conversion result . ...
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... ST92195C/D - VOLTAGE SYNTHESIS TUNING CONVERTER (VS) 7.12 VOLTAGE SYNTHESIS TUNING CONVERTER (VS) 7.12.1 Description The on-chip Voltage Synthesis (VS) converter al- lows the generation of a tuning reference voltage set application. The peripheral is com- posed of a 14-bit counter that allows the conver- sion of the digital content in a tuning voltage, avail- ...