ST92195C STMicroelectronics, ST92195C Datasheet - Page 92

• Manufacturer Part Number: ST92195C
• Description: 48-96 Kbyte Rom Hcmos Mcu With On-screen Display And Teletext Data Slicer
• Manufacturer: STMicroelectronics

TDSRAM (Cont’d)
7.3.4.3 Control Registers
RAM BUFFER CONTROL REGISTER (BUFC)
R248 - Read/Write
Register Page: 38
Reset Value: 0000 1000 (08h)
Bits 7:6 = Reserved, keep in reset state.
Bit 5 = PEF: Parity Error Flag .
This bit is set by hardware, when a parity error has
occurred during the 40 byte transfer (in any write
mode).
PEF has to be reset by software before starting
another MBT.
Bit 4 = BADU: Buffer Address Down/Up .
This bit is set and cleared by software.
0: Address counter in incrementation mode
1: Address counter in decrementation mode
Bits 3:1 = MOD[2:0]: Multi-Byte Transfer Mode
Select Bits .
Programming these bits, allows the user to choose
7
0
0
PEF BADU MOD2 MOD1 MOD0 BUSY
ST92195C/D - TELETEXT DISPLAY STORAGE RAM INTERFACE
0
With the chosen coding, MOD2 serves at the
same time as a buffer read/write signal.
The selected mode is memorised when “BUSY” is
set. Any further modification of the 3 bits will only
be taken into account for the next MBT. The reset
value corresponds to a read access of the RAM.
Bit 0 = BUSY: Multi-Byte Transfer Busy Bit (R/W)
When this bit is set by software, the RAM interface
starts a 40 byte transfer. As long as this “busy flag”
is set, the RAM interface doesn't accept a new
transfer request (buffer is “busy”). BUSY is auto-
matically reset when the transfer has been fin-
ished. The RAM access slots, reserved for the
MBT, are used for direct CPU access when BUSY
is “0”.
MOD2
0
0
0
0
1
MOD1
0
0
1
1
-
MOD0
0
1
0
1
-
Write only
Write with parity reject
Parity cancelled on write
Write with parity reject &
parity cancelled on write
Read only
Selected Mode
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