ADN2817 Analog Devices, Inc., ADN2817 Datasheet - Page 14

• Manufacturer Part Number: ADN2817
• Description: Continuous Rate 10 Mbps To 2.7gb/s Clock And Data Recovery Ics
• Manufacturer: Analog Devices, Inc.

ADN2817/ADN2818
Table 8. Control Register, CTRLA
D7
Set to 0
Set to 0
Set to 1
Set to 1
Table 9. Control Register, CTRLB
Config LOL
D7
0 = LOL pin normal operation
1 = LOL pin is static LOL
Table 10. Control Register, CTRLC
D7
Set to 0
Table 11. Control Register, CTRLD
CDR Bypass
D7
0 = CDR
enabled
1 = CDR
disabled
Table 12. Control Register, CTRLE
D7
Set to 0
Table 13. SEL_MODE
D7
Set to 0
D6
Set to 0
Set to 1
Set to 0
Set to 1
D6
Set to 0
D6
Set to 0
D6
Set to 0
f
REF
Disable DATAOUT
Buffer
D6
0 = data buffer
enabled
1 = data buffer
disabled
Range
10 MHz to 25 MHz
25 MHz to 50 MHz
50 MHz to 100 MHz
100 MHz to 200 MHz
D5
Set to 0
D5
Set to 0
D5
Set to 0
Reset MISC[4]
D6
Write a 1 followed
by 0 to reset MISC[4]
D4
Set to 0
D4
Set to 0
Disable CLKOUT
Buffer
D5
0 = CLK buffer
enabled
1 = CLK buffer
disabled
D4
Set to 0
Data Rate/DIV_FREF Ratio
D5
0
0
0
1
D4
0
0
0
0
D3
Set to 0
D3
Set to 0
D5
Set to 0
n
Initiate Frequency Acq
D5
Write a 1 followed
by 0 to initiate a
frequency acquisition
D3
0
0
1
0
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Set to 0
D4
D2
0
1
0
0
Configure LOS
D2
0 = active high LOS
1 = active low LOS
0
1
All other combinations reserved
D2
2
256
1
4
2
CLK Holdover Mode
D2
Set to 1 for clock holdover mode
n
Initiate PRBS Sequence
Write a 1 followed by 0
to initiate a PRBS generate
sequence
D3
D1
1
0
Measure Data Rate
D1
Set to 1 to measure data rate
D0
0
1
D4
Set
to 0
Function
Enable DDR mode (double data rate mode)
Enable PRBS detector/generator
Reset MISC[2]
D3
Write a 1 followed
by 0 to reset MISC[2]
Squelch Mode
D1
0 = squelch CLK and DATA
1 = squelch CLK or DATA
PRBS/DDR Enable
D2
0
0
1
Lock to REFCLK
D0
0 = lock to input data
1 = lock to reference clock
0
0
0
D1
D1
Set to 0
D2
Set
to 0
PRBS Mode
D0
0
1
0
Function
Power down
PRBS
Generate mode
Detect mode
D1
Set
to 0
D0
Set to 0
D0
Set to 0
D0
Set
to 0