ADN2817 Analog Devices, Inc., ADN2817 Datasheet - Page 8

• Manufacturer Part Number: ADN2817
• Description: Continuous Rate 10 Mbps To 2.7gb/s Clock And Data Recovery Ics
• Manufacturer: Analog Devices, Inc.

ADN2817/ADN2818
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Mnemonic
TEST1
VCC
VREF
NIN
PIN
SLICEP
SLICEN
VEE
THRADJ
REFCLKP
REFCLKN
VCC
VEE
CF2
CF1
LOL
VEE
VCC
SADDR5
SCK
SDA
LOS
VEE
VCC
CLKOUTN
CLKOUTP
SQUELCH
DATAOUTN
DATAOUTP
VEE
Type
P
AO
AI
AI
AI
AI
P
AI
DI
DI
P
P
AO
AO
DO
P
P
DI
DI
DI
DO
P
P
DO
DO
DI
DO
DO
P
NOTES
1. EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE
SLICEP
SLICEN
1
TEST1
VREF
MUST BE CONNECTED TO VEE.
VCC
VEE
NIN
PIN
1
2
3
4
5
6
7
8
Description
Connect to VCC.
Power for Input Stage, LOS.
Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor.
Differential Data Input. CML.
Differential Data Input. CML.
Differential Slice Level Adjust Input.
Differential Slice Level Adjust Input.
GND for the Limiting Amplifier (Limamp), LOS.
LOS Threshold Setting Resistor.
Differential REFCLK Input. 10 MHz to 200 MHz.
Differential REFCLK Input. 10 MHz to 200 MHz.
VCO Power.
VCO GND.
Frequency Loop Capacitor.
Frequency Loop Capacitor.
Loss of Lock Indicator. Active high, LVTTL.
FLL Detector GND.
FLL Detector Power.
Slave Address Bit 5.
I
I
Loss of Signal Detect Output. Active high, LVTTL.
Output Buffer, I
Output Buffer, I
Differential Recovered Clock Output. CML.
Differential Recovered Clock Output. CML.
Disable Clock and Data Outputs. Active high, LVTLL.
Differential Recovered Data Output. CML.
Differential Recovered Data Output. CML.
Phase Detector, Phase Shifter GND.
2
2
C Clock Input.
C Data Input.
32
9
ADN2817/ADN2818
Figure 5. Pin Configuration
31
10
Rev. 0 | Page 8 of 36
30
11
(Not to Scale)
TOP VIEW
29
12
2
2
C GND.
C Power.
28
13
27
14
26
15
25
16
24
23
22
21
20
19
18
17
VCC
VEE
LOS
SDA
SCK
SADDR5
VCC
VEE