ADN2817 Analog Devices, Inc., ADN2817 Datasheet - Page 19

• Manufacturer Part Number: ADN2817
• Description: Continuous Rate 10 Mbps To 2.7gb/s Clock And Data Recovery Ics
• Manufacturer: Analog Devices, Inc.

FUNCTIONAL DESCRIPTION
FREQUENCY ACQUISITION
The ADN2817/ADN2818 acquire frequency from the data over
a range of data frequencies from 10 Mbps to 2.7 Gbps. The lock
detector circuit compares the frequency of the VCO and the
frequency of the incoming data. When these frequencies differ
by more than 1000 ppm, LOL is asserted. This initiates a fre-
quency acquisition cycle. The VCO frequency is reset to the
bottom of its range, which is 10 MHz. The frequency detector
compares this VCO frequency and the incoming data frequency
and increments the VCO frequency, if necessary. Initially, the
VCO frequency is incremented in large steps to aid fast acquisi-
tion. As the VCO frequency approaches the data frequency, the
step size is reduced until the VCO frequency is within 250 ppm
of the data frequency, at which point LOL is deasserted.
Once LOL is deasserted, the frequency-locked loop is turned
off. The phase- and delay-locked loop (PLL/DLL) pulls in the
VCO frequency until the VCO frequency equals the data
frequency.
The frequency loop requires a single external capacitor between
CF1 and CF2, Pin 14 and Pin 15. A 0.47 μF ± 20%, X7R ceramic
chip capacitor with <10 nA leakage current is recommended.
Leakage current of the capacitor can be calculated by dividing
the maximum voltage across the 0.47 μF capacitor, ~3 V, by the
insulation resistance of the capacitor. The insulation resistance
of the 0.47 μF capacitor should be greater than 300 MΩ.
LOCK DETECTOR OPERATION
The lock detector on the ADN2817/ADN2818 has three modes
of operation: normal mode, REFCLK mode, and static LOL mode.
Normal Mode
In normal mode, the ADN2817/ADN2818 function as
continuous rate CDRs that lock onto any data rate from
10 Mbps to 2.7 Gbps without the use of a reference clock as
an acquisition aid. In this mode, the lock detector monitors
the frequency difference between the VCO and the input data
frequency, and deasserts the loss of lock signal that appears on
LOL Pin 16 when the VCO is within 250 ppm of the data
frequency. This enables the delay- and phase-locked loop
(DLL/PLL), which pulls the VCO frequency in the remaining
amount and acquires phase lock. When locked, if the input
frequency error exceeds 1000 ppm (0.1%), the loss of lock signal
is reasserted and control returns to the frequency loop, which
begins a new frequency acquisition starting at the lowest point
in the VCO operating range, 10 MHz. The LOL pin remains
asserted until the VCO locks onto a valid input data stream to
within 250 ppm frequency error. This hysteresis is shown in
Figure 30.
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LOL Detector Operation Using a Reference Clock
In this mode, a reference clock is used as an acquisition aid to
lock the ADN2817/ADN2818 VCO. Lock to reference mode is
enabled by setting CTRLA[0] to 1. The user also needs to write
to the CTRLA[7:6] and CTRLA[5:2] bits to set the reference
frequency range and the divide ratio of the data rate with
respect to the reference frequency. For more details, see the
Reference Clock (Optional) section. In this mode, the lock
detector monitors the difference in frequency between the
divided down VCO and the divided down reference clock.
The loss of lock signal, which appears on the LOL Pin 16, is
deasserted when the VCO is within 250 ppm of the desired
frequency. This enables the DLL/PLL, which pulls the VCO
frequency in the remaining amount with respect to the input
data and acquires phase lock. Once locked, if the input fre-
quency error exceeds 1000 ppm (0.1%), the loss of lock signal
is reasserted and control returns to the frequency loop, which
reacquires with respect to the reference clock. The LOL pin
remains asserted until the VCO frequency is within 250 ppm of
the desired frequency. This hysteresis is shown in Figure 30.
Static LOL Mode
The ADN2817/ADN2818 implement a static LOL feature, which
indicates if a loss of lock condition has ever occurred and remains
asserted, even if the ADN2817/ADN2818 regain lock, until the
static LOL bit is manually reset. The I
the static LOL bit. If there is ever an occurrence of a loss of lock
condition, this bit is internally asserted to Logic high. The
MISC[4] bit remains high even after the ADN2817/ADN2818
reacquire lock to a new data rate. This bit can be reset by
writing a 1 followed by 0 to I
reset, the MISC[4] bit remains deasserted until another loss of
lock condition occurs.
Writing a 1 to I
Pin 16, to become a static LOL indicator. In this mode, the LOL
pin mirrors the contents of the MISC[4] bit and has the function-
ality described in the previous paragraph. The CTRLB[7] bit
defaults to 0. In this mode, the LOL pin operates in the normal
operating mode, that is, it is asserted only when the ADN2817/
ADN2818 are in acquisition mode and deasserts when the
ADN2817/ADN2818 reacquire lock.
–1000
2
C Register Bit CTRLB[7] causes the LOL pin,
Figure 30. Transfer Function of LOL
–250
1
0
2
C Register Bit CTRLB[6]. When
LOL
ADN2817/ADN2818
250
2
C register bit, MISC[4], is
1000
f
(ppm)
VCO
ERROR